Abstract: A present invention novel frequency-phase discriminator has input channels for real and imaginary data which are coupled to two programmable despreaders. The first despreader has its real and imaginary outputs coupled to individual programmable data rate filters which have their individual outputs coupled to a quadrant detector that generates a phase angle direction signal and sign magnitude. The second despread has its real and imaginary outputs connected through individual programmable inverters to data rate filters which have their individual outputs coupled to a quadrant selector that selects error signal data rate information from one of four quadrant axes signals. A command generator is programmably coupled to the output of the quadrant detector and to the input of the quadrant selector and provides a selection signal to the quadrant selector which produces a frequency error signal output employed in a frequency lock loop or in a phase lock loop.

Abstract: Apparatus for generating a complex composite code for fast acquisition by multiple access users is provided which comprises a composite code generator having an in-phase channel code generator and a quadrature channel code generator for generating two linear composite codes. The quadrature channel composite code is modulated onto a carrier which is 90.degree. out of phase with the in-phase carrier. The two linear composite codes are summed together and simultaneously transmitted to the receivers. Each receiver has a plurality of components code generators which generate replica component codes for fast acquisition of the composite code. A plurality of the components codes of the in-phase composite code are derived from the like components code generators in the quadrature channel to enhance speed of acquisition without acknowledgements by the receivers that any of the components codes have been acquired.

Abstract: A novel digital variable rate clock synthesizer is provided with a novel fractional-N digital phase locked loop. The all digital phase locked loop employs a digital input signal to a phase comparator which has a second input coupled to a digital control oscillator through a divide by N or a divide N+1 circuit. The digital output of the phase comparator is coupled to an error accumulating circuit which has a phase correction input signal from a fractional register and an associated accumulator. The output from the error accumulator is coupled to a pair of detectors for generating phase and frequency error detection signals which are digitally coupled to the control input of the digital control oscillator to provide a variable frequency output selected by the value of N and N+1.

Abstract: A multiple document detector uses a driven wheel (40) opposed by an idler wheel (44) on a castoring arm (60). The wheels (40,44) each have a coefficient of friction against a document greater than the coefficient of friction of a document against another document. When a sensor (14A,14B) senses the presence of a document (26) a solenoid (70) operates to attract a magnetic slug (58). If only one document (26) is present the idler wheel (44) stays in a preferred position. If two documents are present the solenoid (70) has sufficient force to cause the idler wheel (44) to push one document (26) to slide against another. In doing so the movement of the idler wheel (44) is detected by a microswitch (18) which signals the presence of multiple documents.

Abstract: A fast acquisition coherent code tracking loop for use in direct sequence spread spectrum systems is provided with an embedded frequency offset loop. The frequency offset loop in the code tracking loop is provided with a pair of multipliers, one of which is coupled to the carrier tracking loop through a scaling circuit and the second multiplier is coupled to the output of the highly stable VCO of the carrier tracking loop to provide extremely fast phase acquisition of the received PN code and very high frequency stability of the code tracking loop.

Abstract: A high speed real time print head controller is provided for supporting a high resolution vector graphics command set which is employed to perform flexible high speed generation of textured line effects. Rows of continuous graphics line information are generated by a print head controller and modified by novel texture control means and style control means so that the bit information supplied to a shift alignment means under control of the style logic means is loaded into a bit map memory one parallel word at a time to completely load a page of information in the bit map memory in the desired styled and textured pixel format for presentation to a write head buffer for printout.

Abstract: A plurality of synchronized phase generators are provided in a mainframe computer of the type having unit card each of which contain a plurality of very large scale integrated (VLSI) logic chips. Each logic chip has its own on-chip phase generator which is controlled by off-chip control signals. The on-chip phase generations each comprise output phase control gates coupled to: an on-chip start shift register, a stop shift register, clock shift registers which provide the phase of the clock, and start-stop run controls all of which are coupled to off-chip control signals and to the output phase control gates which are synchronized to eliminate distortion and skew between phase generators on different logic chips.

Abstract: An hermetic integrated circuit package having a single die wherein wire connections to area pads on the active face of the die are carried through an hermetic boundary comprised of a cover plate to an external interface with the next succeeding interconnect level. The package is comprised of a heat exchange element to which the die is attached, a cover plate having holes homologously positioned with respect to the area pads on the die and a seal ring for joining the heat exchange element to the cover plate. The wire connections which are carried through the holes and sealed to the cover plate are externally accessible.

Abstract: A plural clock system for multiple processor configurations is provided which comprises one clock system for each processor. Each pre-synchronized clock system has a strobe unit and multi-phase output generator. Each multi-phase output generator has a strobe input signal, a plurality of phase output signals and an expansion sync output signal. One of the clock systems employs its oscillator as the master oscillator for the master plural clock system and the other pre-synchronized clock systems are coupled to, and synchronized by the expansion sync output signals of other clock systems.

Abstract: A paper holding apparatus suitable for holding undersized paper products in a typewriter mechanism. The paper holder includes two flexible plastic strips mounted on a backing. The strips have opposed recesses in which the undersized paper product may be positioned. The holder is of sufficient size to operate normally in a typewriter mechanism. It may be reusable or disposable depending upon the application.

Abstract: A unified system of programming communication for use on individual computer systems with capacity for generating relevant user specific information simultaneously at each station of a plurality of subscriber stations. The system includes a transmission station which is a central control system of a system of receiver station computers controlled by the station transmission. Each individual computer system is self-structuring in that any given transmission station can transmit control information causing selected apparatus at selected receiver stations to combine the computers at those stations based on the transmission of the station, thereby causing the individual computers to come under control of station. The unified system also includes apparatus for combining the user specific information generated at subscriber station into broadcast programming, so that broadcast programming is displayed at every station with user specific information displayed in the broadcast programming.

Abstract: An improved access panel assembly including a multi-functional frame which enables the door to be mounted within the frame from either opposing face. Also included is a unique locking mechanism which enables the door to be press-fitted within the frame from either face while firmly retaining the door within the frame. The assembly is fabricated from plastic composition material which is highly resistant to environmental conditions, particularly water and humidity.

Abstract: A multiple-loop microwave frequency synthesizer is provided with an upper and a lower phased-lock loop. The phased-lock loops are mutually connected to a novel sampling mixer and their outputs are connected to an up-converter for providing microwave frequency generated signals. The phased-lock loops are provided with a plurality of programmable frequency dividers connected to a processor controller to provide a wide range of adjustable frequencies up to 20 gigahertz at the output of the frequency synthesizer.

Abstract: A high-speed analog multiplier circuit for multiplying two analog inputs comprises a signum generator having an X input multiplier and having an output connected to a high-speed electronic switch. A Y analog input multiplicand is also connected to the high-speed electronic switch and the output of the electronic switch is connected to a differential amplifier of the type having a positive input, a negative input and a resultant output for producing the signum function (X) times Y. The electronic switch is operated by the signum generator so that the presence of a high Q output from the signum generator is effective to connect the Y multiplicand input to the positive input of the differential amplifier and that the presence of a high Q input from the signum generator is effective to connect the Y multiplicand input to the negative input of the differential amplifier.

Abstract: In a two way ranging system of the type employing pseudonoise spread spectrum codes there is provided a method for correcting the navigational system of one of two moving stations in space to compensate for relative drift. The point positions of the two stations are calculated by the on-board navigation systems of the individual stations at a first and subsequently at a second position after relative movement. The range from station 1 to station 2 is calculated employing the highly accurate pseudonoise communications ranging systems. The range uncertainty of the range calculation and the trigonmetric relation of the two calculated ranges and the include angle between the line of sight of the range directions is employed to calculate a range of uncertainty parallelogram more accurate that the navigation systems. When a station's point position is indicated by its navigation system to be outside the parallelogram, the navigation system is corrected to compensate for relative drift.

Abstract: A method of rapidly reacquiring a pseudonoise spread spectrum coded signal after short outages includes calculating the new positions of the moving stations relative to the old positions of the moving stations and for determining the accurate displacement and the accurate direction the platforms have moved in their new direction after a short time outage. The method includes calculating a triangle which includes the displacement between the moving stations' old position and the moving stations new position and the included angle between the direction of movement and the line of sight between said moving platforms at the time of outage. A range displacement adjustment is calculated on the basis of the triangle for each moving station and the range factor resulting from this calculation is applied to the PN generators of the receiver and transmitter in each of the moving stations to independently adjust for each station's movement.

Abstract: Apparatus and a method of generating very very long pseudonoise (PN) spread spectrum codes is provided where the code is so long that it need never repeat itself during actual use. The transmitter is adapted to start to transmit one set of a plurality of component codes as a composite code having correlation properties with the component codes. When the first set of component codes are acquired at the receiver the composite code is then transmitted as a component of a different composite code which contains the previous composite code and a second new set of component codes which have correlation properties with the new set of component codes. When the second set of component codes are acquired by the receiver the composite code is then transmitted as a third new and different composite code which contains a third new set of component codes which have correlation properties with third new set of component codes.

Abstract: A variable rate near perfect rectangular matched filter is provided with a low pass filter coupled to the input symbol data stream. The output of the filter is coupled to a sampler and the output of the sampler is coupled to an analog to digital converter to provide digital samples indicative of the data stream at a time occurring between input data symbols. The output of the analog to digital converter is applied to a digital adder which has a filter correction input factor to adjust the output of the digital adder so that the digital samples approximate very closely the output of a perfect rectangular matched filter.

Abstract: An image reject apparatus for covering a broad range of signal systhesis frequencies is provided with a digital phase shifter having an input for receiving modulated signals at twice the desired output frequency. A modulator comprising a power divider having a radio frequency (RF) input, a pair of mixers coupled to the outputs of said digital phase shifter and to the outputs from said power divider provides mixer output signals which are combined to produce sum and difference product signals as desired side band signals.

Abstract: Apparatus is provided for compressing unfocused synthetic aperture radar (SAR) phase history pixel data by coupling the complex inphase phase history data output from the SAR to a first converter/compressor which produces compressed scalar log amplitude data and scalar phase pixel data. The output from the first converter/compressor is applied to a series to parallel converting means for converting plural scaler pixel data into vector data representative of a plurality of pixels. The output of the series to parallel conversion means is coupled to a second converter/compressor for converting the plural scalar pixel data into compressed encoded data representative of a plurality of pixels of unfocused SAR phase history data which is transmitted as compressed unfocused phase history data.