Abstract: A method and processor chip design for enabling a processor core to continue sending store operations speculatively to the store queue after the core receives indication that the store queue is full. The processor core is configured with speculative store logic that enables the processor core to continue issuing store operations while the store queue full signal is asserted. A copy of the speculatively issued store operation is placed within a speculative store buffer. The core waits for a signal from the store queue indicating the store operation was accepted into the store queue. When the speculatively-issued store operation is accepted within the store queue, the copy is discarded from the buffer. However, when the store operation is rejected, the speculative store logic re-issues the store operation ahead of normal store operations.

Abstract: A technique for verification of a logic design using a liveness-to-safety conversion includes assigning liveness gates for liveness properties of a netlist and assigning a single loop gate to provide a loop signal for the liveness gates. Assertion of the single loop gate is prevented when none of the liveness gates are asserted. A first state of the netlist is sampled and the sampled first state provides an initial state for a first behavioral loop for at least one of the liveness gates following the assertion of the single loop gate. The sampled first state of the first behavioral loop is compared with a later state of the first behavioral loop to determine if the sampled first state is repeated. A liveness violation is returned when the sampled first state is repeated and an associated one of the liveness gates remains asserted for a duration of the first behavioral loop.

Abstract: A method, system, and computer-readable medium embodying a computer program for securing a communication against access by unintended users is presented. A communication is initiated from a person using an originating telecommunication device to an intended receiving wireless telecommunication device. In response to the communication failing to connect to the intended receiving wireless telecommunication device, a telecommunications host carrier provider may re-route the communication to an alternate telecommunication device. A business authentication logic of the host carrier then determines any security or quality of service filters established by the user of the originating telecommunication device prior to the communication being initiated to prevent unintended users from accessing the communication. Upon the business authentication logic of the host carrier authorizing the communication, the communication is encrypted and re-routed to the alternate telecommunication device.

Abstract: In response to a data request, a victim cache line is selected for castout from a lower level cache, and a target lower level cache of one of the plurality of processing units is selected. A determination is made whether the selected target lower level cache has provided more than a threshold number of retry responses to lateral castout (LCO) commands of the first lower level cache, and if so, a different target lower level cache is selected. The first processing unit thereafter issues a LCO command on the interconnect fabric. The LCO command identifies the victim cache line to be castout and indicates that the target lower level cache is an intended destination of the victim cache line. In response to a successful coherence response to the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.

Abstract: A technique for sharing a fabric to facilitate off-chip communication for on-chip units includes dynamically assigning a first unit that implements a first communication protocol to a first portion of the fabric when private fabrics are indicated for the on-chip units. The technique also includes dynamically assigning a second unit that implements a second communication protocol to a second portion of the fabric when the private fabrics are indicated for the on-chip units. In this case, the first and second units are integrated in a same chip and the first and second protocols are different. The technique further includes dynamically assigning, based on off-chip traffic requirements of the first and second units, the first unit or the second unit to the first and second portions of the fabric when the private fabrics are not indicated for the on-chip units.

Abstract: A primary I/O adapter and a redundant I/O adapter of a data processing system are assigned to support access to a system resource. While the primary I/O adapter is in service and the redundant I/O adapter is not in service in providing access to the system resource, a fail over command is issued to remove the primary I/O adapter from service and place the redundant I/O adapter in service in supporting access to the system resource. While the redundant I/O adapter is in service and the primary I/O adapter is not in service in providing access to the system resource, diagnostic testing on the primary I/O adapter is performed. In response to the diagnostic testing revealing no fault in the primary I/O adapter, a fail back command is issued to restore the primary I/O adapter to service and to remove the redundant I/O adapter from service.

Abstract: A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core that specifies a non-modifying access to a target coherency granule, a determination is made whether the memory access request hits or misses in a directory of the lower level victim cache. In response to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state, the lower level victim cache provides the target coherency granule of the memory access request to the upper level cache. The lower level victim cache preserves the target coherency granule in the lower level victim cache in a shared coherence state if the memory access request is of a first type and invalidates the target coherency granule if the memory access request is of a second type.

Abstract: A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.

Abstract: A method, system and computer program product for providing a framework to enable a builder to construct a situational application, wherein the framework provides access to one or more background data sources. A graphical user interface is displayed to receive feedback inputs, including one or more inputs which describe the problem detected within a data item of a situational application, by an end-user. Feedback inputs may include a unique identifier of the problem data item and identification details of the service from which the data originates. A second input may be of a note, which provides suggestions for improving the data within the data item. Preference information is provided to a notification agent within the framework of the situational application about whether the owner of the data allows direct correction of the data and whether feedback input has to be stored in a problem cache.

Abstract: A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s)/site(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below (adjacent to) the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises different mesh configurations from among: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas, and the Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines.

Abstract: A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.

Abstract: A system model of a real-world system includes a multi-level hierarchy of Capabilities, where each Capability includes a Verb specifying an action and an Object acted on by the Verb. The system model also contains one or more multi-level Performer hierarchies, where each Performer hierarchy includes a plurality of Performers each having an associated lifecycle and at least one associated Capability provided or required by the Performer. In addition, a multi-level Location hierarchy associates one of a plurality of Locations with each Performer. A plurality of Capability Instances define requirement and provision of Capabilities by Performers in the one or more multi-level Performer hierarchies. In response to a query specifying a Location and a time, a view of the system model for the specified Location and time is output.

Abstract: A method, system and computer program product records missed information that is communicated between one or more connected communication terminals during a disconnection period and replays the missed information when a temporarily-disconnected communication terminal reconnects to the active communication session. The method comprises: detecting disconnection of the communication terminal from the active communication session; in response to detecting the disconnection, automatically recording the missed information exchanged between the one or more connected communication terminals remaining in the active communication session; detecting reconnection of the disconnected terminal to the active communication session; and delivering the recorded information exchange to the reconnected terminal, in response to detecting the reconnection.

Abstract: A method, computer program product, and data processing system provide an updateable encrypted operating kernel. Secure initialization hardware decrypts a minimal secure kernel containing sensitive portions of data and/or code into a portion of the processor-accessible memory space, from which the kernel is executed. Most system software functions are not directly supported by the secure kernel but are provided by dynamically loaded kernel extensions that are encrypted with a public key so that they can only be decrypted with a private key possessed by the secure kernel. The public/private key pair is processor-specific. Before passing control to a kernel extension, the secure kernel deletes a subset of its sensitive portions, retaining only those sensitive portions needed to perform the task(s) delegated to the kernel extension. Which sensitive portions are retained is determined by a cryptographic key with which the kernel extension is signed.

Abstract: A method of providing visibility of Ethernet components to a subnet manager in a converged InfiniBand over Ethernet (IBOE) network. If a port of an IBOE gateway corresponds to one or more InfiniBand devices, the subnet manager sends fabric management packets (FMPs) to discover the InfiniBand network and assigns physical local identifiers (LIDs) to the InfiniBand devices. If a port of the IBOE gateway corresponds to one or more Ethernet devices, the subnet manager sends FMPs to discover the Ethernet network. The subnet manager adds the Ethernet Media Access Control (MAC) addresses of any responding devices to an LID routing table and assigns LIDs to the Ethernet devices. The subnet manager configures one or more virtual Host Channel Adapters (HCAs) corresponding to the one or more Ethernet MAC addresses in the LID routing table.

Abstract: Within the context of a software factory, process sensors detect time consuming activities that extend beyond an estimated predetermined completion timeline for a project. These process sensors also detect wait states that are caused by processes and activities of tasks that are not critical to completing the project. A process analysis is used to determine if defined added value processes and activities identified in a value stream analysis are interdependent to a critical path for executing the project. If the defined added value processes and activities identified in the value stream analysis are determined to not be interdependent to the critical path for executing the project, then a determination is made that performance of the defined added value processes and activities identified in the value stream analysis is wasteful and such processes and activities are eliminated from the process.

Abstract: A method, computer program product, and data processing system are disclosed for ensuring that applications executed in the data processing system originate only from trusted sources are disclosed. In a preferred embodiment, a secure operating kernel maintains a “key ring” containing keys corresponding to trusted software vendors. The secure kernel uses vendor keys to verify that a given application was signed by an approved vendor. To make it possible for users to execute software from independent software developers, an administrative user may disable the above-described vendor key-checking as an option.

Abstract: A method, system and computer-readable medium for synchronizing databases between two disparate computer systems are presented. In one embodiment, the method includes updating a first database, which is part of a first computer system, with a database update, wherein updating the first database does not initially commit the database update to the first computer system; calling a remote function to incorporate the database update into a second database that is part of a second computer system; in response to the remote function determining that the second database has been successfully updated with the database update, committing the database update to the first computer system; and in response to the remote function determining that the second database has not been successfully updated with the database update, rolling back the database update such that the first computer system is unaware of the attempted updating of the first database.

Abstract: Analyzing pre-processed code includes identifying at least one storage-modifying construct specifying a storage-modifying memory access to a memory hierarchy of a data processing system and determining if more than one granule of a cache line of data containing multiple granules that is targeted by the storage-modifying construct is subsequently referenced by said pre-processed code. Post-processed code including a storage-modifying instruction corresponding to the at least one storage-modifying construct in the pre-processed code is generated and stored.