Abstract: A power supply includes a rectifier having an AC input and a DC output and a power factor correction (PFC) preregulator, coupled to the rectifier, that increases a power factor of the power supply. The PFC preregulator includes a controller that integrates an input power to determine energy consumption and outputs a signal indicative of the energy consumption.

Abstract: A method, system, and computer-readable medium for maintaining a health of a software factory that creates custom software in a standardized manner is presented. In a preferred embodiment, the method includes the steps of: defining work packets to perform sub-functions of a custom software; tracking a transmission of the work packets to an assembly line in a software factory; monitoring any retrieval of software artifacts that are used to create the work packets; monitoring any on-going changes of work activities that are contained in the work packets; determining if execution of the work packets conforms to governance guidelines for the software factory; monitoring the software factory to ensure that the work packets comply with an architecture of the software factory; tracking quality metrics for an execution of the work packets in an assembly line in the software factory; and transmitting all tracked and monitored information described above to a dashboard.

Abstract: A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core, the lower level cache victim determines whether the memory access request hits or misses in the directory of the lower level victim cache, and the upper level cache determines whether a castout from the upper level cache is to be performed and selects a victim coherency granule for eviction from the upper level cache. In response to determining that a castout from the upper level cache is to be performed, the upper level cache evicts the selected victim coherency granule. In the eviction, the upper level cache reads out the victim coherency granule from the data array of the upper level cache only in response to an indication that the memory access request misses in the directory of the lower level victim cache.

Abstract: A processing unit includes a store-in lower level cache having reservation logic that determines presence or absence of a reservation and a processor core including a store-through upper level cache, an instruction execution unit, a load unit that, responsive to a hit in the upper level cache on a load-reserve operation generated through execution of a load-reserve instruction by the instruction execution unit, temporarily buffers a load target address of the load-reserve operation, and a flag indicating that the load-reserve operation bound to a value in the upper level cache. If a storage-modifying operation is received that conflicts with the load target address of the load-reserve operation, the processor core sets the flag to a particular state, and, responsive to execution of a store-conditional instruction, transmits an associated store-conditional operation to the lower level cache with a fail indication if the flag is set to the particular state.

Abstract: In response to receiving pre-processed code, a compiler identifies a code section that is not candidate for acceleration and identifying a code block specifying an iterated operation that is a candidate for acceleration. In response to identifying the code section, the compiler generates post-processed code containing one or more lower level instructions corresponding to the identified code section, and in response to identifying the code block, the compiler creates and outputs an operation data structure separate from the post-processed code that identifies the iterated operation. The compiler places a block computation command in the post-processed code that invokes processing of the operation data structure to perform the iterated operation and outputs the post-processed code.

Abstract: A data processing system includes a mechanism for completing an asynchronous memory move (AMM) operation in which the processor receives an AMM ST instruction and processes a processor-level move of data in virtual address space and an asynchronous memory mover then completes a physical move of the data within the real address space (memory). A status/control field of the AMM ST instruction includes an indication of a requested treatment of the lower level cache(s) on completion of the AMM operation. When the status/control field indicates an update to at least one cache should be performed, the asynchronous memory mover automatically forwards a copy of the data from the data move to the lower level cache, and triggers an update of a coherency state for a cache line in which the copy of the data is placed.

Abstract: A technique for performing an analysis of a logic design includes detecting an initial transient behavior in a logic design embodied in a netlist. A duration of the initial transient behavior is also determined. Reduction information on the logic design is gathered based on the initial transient behavior. The netlist is then modified based on the reduction information.

Abstract: A second lower level cache receives an LCO command issued by a first lower level cache on an interconnect fabric. The LCO command indicates an address of a victim cache line to be castout from the first lower level cache and indicates that the second lower level cache is an intended destination of the victim cache line. The second lower level cache determines whether to accept the victim cache line from the first lower level cache based at least in part on the address of the victim cache line indicated by the LCO command. In response to determining not to accept the victim cache line, the second lower level cache provides a coherence response to the LCO command refusing the identified victim cache line. In response to determining to accept the victim cache line, the second lower level cache updates an entry corresponding to the identified victim cache line.

Abstract: A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, multiple trace status tables are received, each containing a trace error identified by a formal verification engine that was utilized to perform a RT verification on an integrated circuit design. An error causing signal is then recognized for each of the trace errors. For each of error causing signals, two associating signals are identified, and the two associating signals are then utilized to locate a common point of convergence (POC). The POC is further utilized to locate a common point of divergence (POD), and an RT constraint can be generated based on the identified POC and POD. All the generated RT constraints are applied to constrain the integrated circuit design such that the integrated circuit design is able to pass RT verifications in the future without any timing violations.

Abstract: A method for switching connections between an IP-only phone and a soft phone to an IP gateway server is disclosed. An identical telephone number is allocated to the IP-only phone and the soft phone. When the soft phone has been moved such that a connection destination to a local-area network changes from a first connector to a second connector, a relay device is also changed from a first relay device to a second relay device. After recognizing its present position by a MAC address of the relay device to which it is currently connected, the soft phone issues a request to an IP gateway server to change an IP address to the soft phone when it is determined that the soft phone is located far away from the IP-only phone. When it is determined that the soft phone is located near the IP-only phone, the soft phone issues a request to the IP gateway server so that the IP address is changed to the IP-only phone.

Abstract: A mechanism is provided in a multi-core environment for assigning a globally unique core identifier. A Power PC® processor unit (PPU) determines an index alias corresponding to a natural index to a location in local storage (LS) memory. A synergistic processor unit (SPU) corresponding to the PPU translates the natural index to a first address in a core's memory, as well as translates the index alias to a second address in the core's memory. Responsive to the second address exceeding a physical memory size, the load store unit of the SPU truncates the second address to a usable range of address space in systems that do not map an address space. The second address and the first address point to the same physical location in the core's memory. In addition, the aliasing using index aliases also preserves the ability to combine persistent indices with relative indices without creating holes in a relative index map.

Abstract: In a communication network, links in a transmission path between source and destination terminals are sequentially switched to an operational state in response to a command or a group of commands for transmitting data prior to completion of assembling the data. Each node in the transmission path independently monitors transmission of data. After transmitting the data, the links are selectively switched to pre-determined power saving states.

Abstract: Method, system, and computer program product for instantiating a template in a composite application infrastructure. A template that describes a composite application having a plurality of application components is created. The template includes a composite application component assembly descriptor which lists each application component of the composite application. The template is stored in a template library. The composite application is instantiated using the template for creating at least one composite application instance. In an application instance registry, composite application instance(s) and instance information related to the composite application instance(s) is/are registered. The composite application instances are transiently represented in the application instance registry by a respective table entry without creating a real object. The real object that is dynamically created represents a particular composite application instance during a composite application usage session.

Abstract: In response to a data request of a first of a plurality of processing units, the first processing unit selects a victim cache line to be castout from the lower level cache of the first processing unit and determines whether a mode is set. If not, the first processing unit issues on the interconnect fabric an LCO command identifying the victim cache line and indicating that a lower level cache is the intended destination. If the mode is set, the first processing unit issues a castout command with an alternative intended destination. In response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache, and the victim cache line is held elsewhere in the data processing system. The mode can be set to inhibit castouts to system memory, for example, for testing.

Abstract: Improvements are provided in a service registry in SOA and in service propagation, query, and service selection and routing methods during service invocation. The service registry is connected with a local service domain and a remote service registry and comprises: a local service information manager for registering local services in the local service domain; and a local service information repository connected with the local service information manager for storing service metadata of the local services. The service registry further comprises: a remote service information manager connected with the local service information manager and the remote service registry for receiving a remote service index from the remote service registry; and a remote service information repository connected to the remote service information manager for storing the remote service index received from the remote service registry.

Abstract: A method, a system and a computer program product for defining manageable component objects to an application utilizing data roots. A manageable component engine creates a bridge manageable component model utilizing the data roots. Data roots, or root data, are retrieved and stored in a manageable component persistent index of an application. The manageable component persistent index is processed for one or more root objects during an initialization of a manageable component engine. The manageable component engine queries one or more data sources, and accesses data required for creating a manageable component object instance. One or more manageable component objects are registered in a manageable component repository. The manageable component bridge model is created and displayed via a graphical user interface.

Abstract: A Method of batch processing a group of hardcopy documents scans a stack of documents. Each document in the stack has a cover sheet is placed thereon. The method performs optical character recognition on each of the cover sheets in the stack. The method performs an operation on each of the documents in the stack in accordance with instructions on the cover sheet on each document. Examples of operations that may be performed include printing the document, sending the document by fax to a recipient, sending an image file of the document by email to a recipient, and the like.

Abstract: A method, system, and computer program product for issuing an alert when a method of a live demonstration deviates from demonstration simulation actions. A computer receives a command to commence a demonstration simulation. During the demonstration simulation, capture logic of a computer is initialized. The capture logic records events of the demonstration simulation. When a live demonstration subsequently initiated, demonstration verification logic of the computer continually monitors, in real-time, events of the live demonstration and compares the events to the previously recorded events captured during the demonstration simulation. In response to detecting that a live demonstration has deviated from the recorded demonstration simulation method, the demonstration verification logic issues a non-invasive alert. The non-invasive alert may be issued using visual, audible, or vibration feedback cues in such manner that an audience observing the live demonstration is un-aware of the non-invasive alert.

Abstract: A system, computer-implementable method, and computer-readable medium for improving sequential serial attached small computer system interface storage device performance. According to a preferred embodiment, a microprocessor within a target device receives a collection of tasks from at least one initiator device via a collection of initiator paths. The target device is a cyclic non-volatile memory medium. The microprocessor queues the collection of tasks according to a collection of task list. Each task list corresponds to a respective initiator path. The microprocessor combines the collection of tasks in an execution queue. The collection of tasks on the execution queue is reordered based on a priority scheme. The microprocessor executes the collection of tasks from the execution queue.

Abstract: A system, method, and program for managing a user key used to sign a message for a data processing system having an encryption chip are disclosed. A user is assigned a user key. In order to encrypt and send messages to a recipient(s), the messages are encrypted with the user key. The user key, in turn, is encrypted with an associated key. The associated key is further encrypted using an encryption chip key stored on the encryption chip. The encrypted messages are communicated to a recipient to validate an association of the user with the encrypted messages. The associated key is decrypted with the encryption chip key. The user key is decrypted with the associated key, and the messages are decrypted with the user key. Thereafter, validation of the association of messages with the user is removed by revoking the associated key. In a preferred embodiment, encryption resources are centralized in a server system having the encryption chip.