Abstract: To realize an autonomic system and method of improving the quality of a piece of software and solving problems with respect to operations in stages of a software life cycle. There are provided a pattern catalog 20 in which information on execution environments 11 to 14 in the stages of the software life cycle and information on patterns of design applicable in respective the stages of the software life cycle are stored, a pattern combination search engine 30 which searches the patterns with respect to each of the stages in the pattern catalog 20 on the basis of predetermined conditions including a design objective, and a pattern application agent 40 which applies some of the patterns found by searching performed by the pattern combination search engine 30 and controls the operation in the execution environments 11 to 14. Patterns which accord with the design objective are automatically selected to autonomically improve the quality of the piece of software.

Abstract: Systems, methods, and computer program products for facilitating synchronized, two-way communications between a server application and one or more client applications. In one embodiment, the server application and client applications are provided with instant messaging (IM) clients that are supported by an IM server in a networked computing environment. A method disclosed includes registering at least one client application IM client in an IM registry, generating an event in the server application, and converting the event into an operation command that is independent of the states of the server or client applications. The method can also include transmitting the command to each client application IM client. The method can also include, at the client application, receiving the command, reconstituting an event from the command, and processing the event.

Abstract: A technique for performing a discrete Fourier transform (DFT) includes storing, in a single-port memory, multiple signal points. A first group of consecutive ones of the multiple signal points are fetched (from a first line of the single-port memory) to a first input register associated with a processor that includes multiple arithmetic units (AUs) that are each configured to perform multiply accumulate (MAC) operations. A second group of consecutive ones of the multiple signal points are then fetched (from a second line of the single-port memory) to a second input register associated with the processor. Selected pairs of the multiple signal points are then loaded (one from each of the first and second input registers for each pair) into the multiple arithmetic units during an initial butterfly stage. Radix-2 butterfly operations are then performed on the selected pairs of the multiple signal points (using the multiple AUs) to provide respective output elements.

Abstract: A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.

Abstract: Embodiments of the present invention improve probes and probe assemblies. In one embodiment, the present invention includes a probe test head comprising a plurality of novel probes inserted in an array of holes in upper and lower dies of the assembly. The novel assembly includes a novel alignment layer for easy repair and maintenance of the probes.

Abstract: A data recovery circuit includes a pulse width indicator circuit, an edge detection circuit and a first storage. The pulse width indicator circuit is configured to receive, at an input, a data stream and provide pulses, at respective outputs, that are indicative of respective data bits in the received data stream. The edge detection circuit is configured to receive, on respective inputs, the pulses from the pulse width indicator circuit and provide respective storage signals, on respective outputs that are indicative of a logic level of the respective data bits, responsive to the pulses. The first storage is configured to receive and store the respective storage signals.

Abstract: A method, system, and computer program product for detecting and mapping activity occurring at and between devices on a computer network for utilization within an intrusion detection mechanism. An enhanced graph matching intrusion detection system (eGMIDS) utility executing on a control server provides data collection functions and data fusion techniques. The eGMIDS comprises multiple sensors and associated unique adaptors that are located at different remote devices of the network and utilized to detect specific types of activity occurring at the respective devices relevant to eGMIDS processing. The sensors convert the data into eGMIDS format and encapsulate the data in a special transmission packet that is transmitted to the control server.

Abstract: In at least one embodiment, a processor detects during execution of program code whether a load instruction within the program code is associated with a hint. In response to detecting that the load instruction is not associated with a hint, the processor retrieves a full cache line of data from the memory hierarchy into the processor in response to the load instruction. In response to detecting that the load instruction is associated with a hint, a processor retrieves a partial cache line of data into the processor from the memory hierarchy in response to the load instruction.

Abstract: A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes.

Abstract: In a method of and system for discovering people with attributes, users tag people in their respective contact lists with attribute tags. The method aggregates in a folksonomy database the people tagged in the contact lists. A user may request a list of people tagged with an attribute. In response to a user request, the method searches the folksonomy database for people tagged with the attribute tag. The method returns to the requesting user a list of people tagged with the attribute tag.

Abstract: A data processing system includes an input/output (I/O) host bridge to which at least one I/O adapter is coupled by an I/O link. In a register of the I/O host bridge, a configuration partitionable endpoint (PE) field is set to identify a PE to be used for an I/O configuration operation. Thereafter, the host bridge initiates the I/O configuration operation on the I/O link and determines if an error occurred for the I/O configuration operation. In response to a determination that an error occurred for the I/O configuration operation, an error state is set in the I/O host bridge only for the PE indicated in the configuration PE field of the register in the I/O host bridge, wherein I/O configuration errors are isolated to particular PEs.

Abstract: A method, a system and a computer program product for determining one or more characteristics of a caller, such as the mood, gender, age, and urgency of the caller, utilizing the biometric characteristics of the caller. One or more biometric characteristics are detected when a request to place an outgoing call to one or more destinations is received at a first telecommunication device. When the request to place an outgoing call is a verbal request, one or more biometric voice samples are obtained. The biometric voice samples comprise the biometric characteristics of the caller. The biometric characteristics are extracted from the biometric voice samples, encoded into a datagram, and transmitted from the first telecommunication device to the outgoing call destination (i.e. a second telecommunication device).

Abstract: A data processing system includes a power supply, a plurality of processors wherein each processor is separately powerable by the power supply under operating system control. The operating system determines periodically a measure of system utilization and controls the switches to alter the number of active (powered) processors where the number of active processors reflects the measured system utilization and a set of utilization threshold values. System utilization may be based on the number of active tasks. The utilization thresholds preferably include a maximum threshold and a minimum threshold. A measured utilization exceeding the maximum threshold causes an increase in the number of active processors while utilization less than the minimum threshold causes a decrease in the number of active processors. The utilization thresholds may be determined from threshold factors that reflect time and date information, quality of service information, or a weighted average of historical utilization values.

Abstract: A method, system and computer program product for optimizing allocation of resources to partitions of a data processing system are disclosed. The method includes creating a first virtual central processing unit and a second virtual central processing unit, wherein at least one of the set of the first virtual processing unit and the second virtual processing spans across a first physical processing unit and a second physical processing unit. One or more resources from the first and second virtual central processing units are allocated to a first partition and a second partition. Whether one or more processes running on the first partition can utilize additional resources is determined. One or more resources from the first virtual central processing unit and resources from the second virtual central processing unit are reallocated to the first partition, wherein at least one of the resources was previously allocated to the second partition.

Abstract: A method, system, and computer program product for optimizing power consumption of an executing processor executing. The method includes determining a first sensitivity relationship (SR) based on a first and a second performance metric value (PMV) measured at a first and second operating frequency (OF), respectively. The first SR predicts workload performance over a range of OFs. A third OF is determined based on the first SR and a specified workload performance floor. A third PMV is measured by executing the processor operating at the third OF. A second SR based on the second and third PMVs is then determined. The first and second SRs are logically combined to generate a third SR. Based on the third SR, a fourth OF is outputted.

Abstract: A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned.

Abstract: A handgrip includes a tubular grip body having at least two angularly spaced-apart resilient clamp portions projecting outwardly and axially from an annular end thereof, a substantially U-shaped rod member having a bight portion, and non-threaded head and threaded end portions, and a sleeve ring sleeved around the resilient clamp portions and having first and second curved retaining grooves receiving respectively the resilient clamp portions, a head-receiving groove section receiving the non-threaded head portion, and a guide groove section receiving the threaded end portion. A nut member is disposed outwardly of the guide groove section, and engages threadedly the threaded end portion. The nut member pulls the threaded end portion when tightened so that the bight portion pushes one of the resilient clamp portions toward the other resilient clamp portion.

Abstract: In a global shared memory (GSM) environment, a method provides local notification of completion of a global shared memory (GSM) operation processed by a first task executing at a local node of the distributed system. The system includes multiple nodes on which different tasks of a single job execute and perform GSM operations that are received from a second task via a via host fabric interface (HFI) and associated HFR window assigned to the first tasks. The local task initiates execution of a GSM operation on the local node. The task then monitors for and detects a completion of the execution of the GSM operation on the local node. When the task detects completion of the execution of the GSM operation, the task issues an internal notification to inform the locally-executing tasks of the completion of the GSM operation.

Abstract: A method, processor, and data processing system for implementing a framework for priority-based scheduling and throttling of prefetching operations. A prefetch engine (PE) assigns a priority to a first prefetch stream, indicating a relative priority for scheduling prefetch operations of the first prefetch stream. The PE monitors activity within the data processing system and dynamically updates the priority of the first prefetch stream based on the activity (or lack thereof). Low priority streams may be discarded. The PE also schedules prefetching in a priority-based scheduling sequence that corresponds to the priority currently assigned to the scheduled active streams. When there are no prefetches within a prefetch queue, the PE triggers the active streams to provide prefetches for issuing. The PE determines when to throttle prefetching, based on the current usage level of resources relevant to completing the prefetch.

Abstract: A method, system and computer program product for reducing power consumption when processing mathematical operations. Power may be reduced in processor hardware devices that receive one or more operands from an execution unit that executes instructions. A circuit detects when at least one operand of multiple operands is a zero operand, prior to the operand being forwarded to an execution component for completing a mathematical operation. When at least one operand is a zero operand or at least one operand is “unordered”, a flag is set that triggers a gating of a clock signal. The gating of the clock signal disables one or more processing stages and/or devices, which perform the mathematical operation. Disabling the stages and/or devices enables computing the correct result of the mathematical operation on a reduced data path. When a device(s) is disabled, the device may be powered off until the device is again required by subsequent operations.