Abstract: A transceiver architecture can contain an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data based on a product code of an E8 lattice based on binary and non binary codes that creates an extended Hamming code of a multi-level structure of E8 with four bit estimates. During decoding the multi-level E8 decoding is performed on the Hamming code and then row decoding and column decoding are performed. Then lattice decoding is performed on the output of the row and column decoding. This decoding process can be iteratively performed a predetermined number of times until the encoded bits are decoded.

Abstract: Techniques for multiplexing and demultiplexing signals for optical transport networks are presented. A network component comprises a multiplexer component that multiplexes a plurality of signals having a first signal format to produce a multiplexed signal in accordance with a second signal format, while maintaining error correction code (ECC) of such signals and without decoding such signals and associated ECC. The multiplexer component interleaves the plurality of signals with stuffing and adds overhead without generating new ECC. A second network component receives the multiplexed signal as part of a frame in accordance with the second signal format. A demultiplexer component of the second network component demultiplexes the multiplexed signal using the original ECC associated with the plurality of signals, wherein the second network element removes and filters the stuffing from the multiplexed signal and produces a plurality of demultiplexed signals as an output, in accordance with the first signal format.

Abstract: Various aspects facilitate error reduction for an analog to digital converter (e.g., due to metastability). A digital to analog converter generates a scaled reference voltage based on a reference voltage. A comparator component performs a comparison between an input voltage and the scaled reference voltage based on a defined period of time to perform the comparison.

Abstract: Various embodiments provide for a system that integrates 64 bit ARM cores and a switch on a single chip. The RISC style processors use highly optimized sets of instructions rather than the specialized set of instructions found in other architectures (e.g., x86). The system also includes multiple high bandwidth ports that enable multi-ported virtual appliances to be built using a single chip. The virtual appliances are software implemented versions of the physical appliances that are installed with servers to provide network services such routing and switching services, firewall, VPN, SSL, and other security services, as well as load balancing. The virtual appliances are implemented in software and the system can add new virtual appliances, or change the functions performed by existing virtual appliances flexibly without having to install or remove physical hardware.

Abstract: Various aspects facilitate gain adjustment associated with an analog to digital converter. A capacitor array comprises a plurality binary-weighted capacitors and generates an output voltage received by a comparator based on an input voltage and a reference voltage. A gain calibration component receives the input voltage and applies a modified input voltage that corresponds to a portion of the input voltage to the output voltage generated by the capacitor array component.

Abstract: Various embodiments provide for a system on a chip or a server on a chip that performs flow pinning, where packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor/multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet interface in parallel. Each of the queues can issue interrupts to their assigned processors, allowing each of the processors to receive packets from their respective queues at the same time. Packet processing speed is therefore increased by receiving and processing packets in parallel for different streams.

Abstract: Various aspects provide for mapping a plurality of signals to generate a combined signal. An aggregation component is configured for generating a combined signal that comprises a higher data rate than a data rate associated with a plurality of signals based on mapped data associated with the plurality of signals. The aggregation component comprises a mapper component. The mapper component is configured for generating the mapped data based on a mapping distribution pattern associated with a generic mapping procedure. In an aspect, a de-aggregation component is configured for recovering the plurality of signals from a pseudo signal transmitted at a data rate of the combined signal. In another aspect, the de-aggregation component comprises a de-mapper component configured for de-mapping the mapped data based on the mapping distribution pattern associated with the generic mapping procedure.

Abstract: Various aspects provide a high frequency voltage supply monitor capable of monitoring high frequency variations of the voltage supply inside a microelectronic circuit substantially in real time. The voltage supply monitor can comprise a differential amplifier circuit having a substantially constant gain over a wide bandwidth, allowing the supply voltage variations to be amplified according to a known gain under a wide range of conditions. The amplified signal can then be sent to an output port for monitoring and measurement by an external display device.

Abstract: Various aspects of the present disclosure provide for a system that is able to boot from a variety of media that can be connected to the system, including SPI NOR and SPI NAND memory, universal serial bus (“USB”) devices, and devices attached via PCIe and Ethernet interfaces. When the system is powered on, the system processor is held in a reset mode, while a microcontroller in the system identifies an external device to be booted, and then copies a portion of boot code from the external device to an on-chip memory. The microcontroller can then direct the reset vector to the boot code in the on-chip memory and brings the system processor out of reset. The system processor can execute the boot code in-place on the on-chip memory, which initiates the system memory and the second stage boot loader.

Abstract: Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.

Abstract: System and method of calibrating the DC offsets of alternate comparators in an ADC in the background based on the digital outputs of the ADC. In parallel with A/D conversion of a plurality of samples, the calibration logic uses two counters to count the occurrences of the ADC outputs that represent samples falling in a first analog range and a second analog range, respectively. The two ranges are symmetric about the MSB reference voltage and in combination cover the nominal voltage range of the bit. The DC offset is derived based on a ratio of the difference between the two counts and a sum of the two counts. The calibration logic may alternately calibrate the comparators. Each comparator may be calibrated successively based on various bits associated therewith.

Abstract: Techniques for calibrating interleaved analog-to-digital converter (ADC) arrays are presented. A transceiver comprises an ADC component comprising an array of interleaved sub-ADCs, and an auxiliary path associated with an auxiliary sub-ADC used to facilitate calibrating a sampling array by comparing the auxiliary path signal to signals of the sub-ADCs in the array. A calibration component employs a phase-interpolator and analog delay lines to adjust the auxiliary sub-ADC to enable the auxiliary sub-ADC to be lined up to any one of the sampling instants of the sampling array. The calibration component compares the auxiliary signal to sub-ADC signals, determines path differences between the sub-ADC paths based on the comparison results, and calibrates the sub-ADCs and sub-ADC paths to reduce the path differences to mitigate distortion in a digital stream produced from combining the digital substreams produced by the sub-ADCs in the array.

Abstract: A transceiver architecture contains an encoder and a decoder for communicating high speed transmissions. The encoder modulates signal data based on an FEC code that has a symbol size that is not matched to a symbol size of a hexacode. Any code where the symbol size is less than the sample size for coding can be serially concatenated. During decoding the multilevel decoding leech lattice and FEC decoder iteratively passes their outputs back and forth to each other until the encoded bits are decoded.

Abstract: A decoupling capacitor circuit design facilitates high operational frequency without sacrificing area efficiency. In order to disassociate the sometimes opposing design criteria of high operational frequency and area efficiency, a p-channel field effect transistor (PFET) and an n-channel field effect transistor are connected in a half-cross-coupled (HCC) fashion. The HCC circuit is then supplemented by at least one area efficient capacitance (AEC) device. The half-cross-coupled transistors address the high frequency design requirement, while the AEC device(s) address the high area efficiency requirement. The design eliminates the undesirable trade-off between operating frequency and area efficiency inherent in some conventional DCAP designs.

Abstract: A hardware SATA virtualization system without the need for backend and frontend drivers and native device drivers is disclosed. A lightweight SATA virtualization handler can run on a specialized co-processor and manage requests enqueued by individual guest devices or virtual machines (VMs). The lightweight SATA virtualization handler can also perform the scheduling or queuing of the requests based on performance optimizations to reduce seek time as well as based on the priority of the requests. The specialized co-processor can communicate to an integrated SATA controller through an advanced host controller interface (“AHCI”) data structure that is built by the coprocessor and has commands from one or more VMs. Guest devices or guest operating systems can build associated AHCI data structures in memory, which may be on-chip memory or DDR memory.

Abstract: Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, a forced halt sequence can be initiated, which causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.

Abstract: Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.

Abstract: Systems and methods of mitigating precursor ISIs for communication channels having time-variant precursor channel responses using digital circuit designs. A phase adaptation circuit is utilized in a receiver and configured to generate a phase control signal responsive to an input signal and based on the current precursor channel response. The phase control signal controls the phase shift of a recovered clock to a position where the precursor ISI at h(?1) is minimized. The phase control signal corresponds to a “feed-forward equalization (FFE) first tap weight” obtained via a digital least-mean-square (LMS) process.

Abstract: Various aspects provide for generating a clock signal for a hold latch. A latch pulse generator generates a pulse clock signal based on a first clock signal associated with a first flip-flop component and a second clock signal associated with a second flip-flop component. A hold latch component receives the pulse clock signal generated by the latch pulse generator and generates a data signal that is transmitted to the second flip-flop component.

Abstract: Various aspects provide for generating a timeout signal based on a clock counter associated with a data request. An interface component is configured for receiving a data request from a master device and forwarding the data request to a slave device. A timeout component is configured for maintaining a clock counter associated with the data request and generating a timeout signal in response to a determination that a threshold level associated with the clock counter is reached before receiving a data response associated with the data request from the slave device.