Abstract: Systems and methods for generating gapped signals comprising a Delta Sigma Modulator (DSM) configured to generate gapping control signals used to control gap removal rates of an associated gapping unit. The DSM is configured to generate a gapping control signal based on a value of an overflow resulted from performing adding a first number with a remainder of a stored value modulo a second number. The gap removal rates as well as the gap removal resolutions can be adjusted by selecting appropriate values of the first number, the stored value, and the second number. The gapping resolution can be a portion of a pulse. The first number and the second number may be derived from an intended frequency ratio between a gapped signal and a corresponding input signal. The gapping unit may comprise a gapping circuit or a multi-modulus divider.

Abstract: Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.

Abstract: Discrete time compensation mechanisms include a channel component configured for determining which channel of a plurality of channels to process time slots of sampled data that are time stamped in a discrete time and processing the time slots of the sampled data to the plurality of channels. A common channel clock component is configured for time stamping the time slots of the sampled data in the discrete time domain that is faster than a non-discrete reference time stamp of continuous data from which the time slots are sampled from and for processing the sampled data through the plurality of channels faster than the continuous data is being received. Compensations for one or more gaps are generated based on a set of predetermined criteria and a corrected time stamp is applied to the sampled data for processing among different processing channels.

Abstract: Systems and methods are provided that facilitate memory storage in a multi-bank memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends commands to the memory array and the memory array updates or retrieves data contained therein based upon the command. If the memory controller detects a pattern of memory requests, the memory controller can issue a preemptive activation request to the memory array. Accordingly, memory access overhead is reduced.

Abstract: A method is provided for pre-fetching packet data prior to processing. The method accepts a plurality of packets and writes each packet into a memory. A message is derived for each packet, where each message includes a packet descriptor with a pointer to an address of the packet in the memory. Each message is added to a tail of a first-in first-out (FIFO) queue. A pre-fetch module examines a first message, if the first message reaches a first capacity threshold of the FIFO queue. If the first message reaches the first capacity threshold, the pre-fetch module reads a first packet associated with the first message, from the memory, and the first packet is loaded into cache memory. A processor reads the first message from a head of the FIFO queue, and in response to reading the first message, reads the previously loaded first packet from cache memory.

Abstract: Systems and methods for detecting defect propagation in a networked environment comprising a defect detection component to detect defects in an aggregate signal and/or in individual signals; and a replacement signal component to generate a maintenance signal to replace defective signals detected by the defect detection component. The maintenance signal can be a uniform signal type regardless of a type associated with a defective signal. The maintenance signal can replace a defective signal during aggregation, by an aggregation component.

Abstract: Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor. On applying a control voltage to the third transistor and applying an input voltage to the first control port, the second control port is selectively modified by the control voltage to produce a desired output at the first input port and the second input port.

Abstract: Various aspects provide large receive offload (LRO) functionality for a system on chip (SoC). A classifier engine is configured to classify one or more network packets received from a data stream as one or more network segments. A first memory is configured to store one or more packet headers associated with the one or more network segments. At least one processor is configured to receive the one or more packet headers and generate a single packet header for the one or more network segments in response to a determination that a gather buffer that stores packet data for the one or more network segments has reached a predetermined size.

Abstract: Systems and methods for frequency synthesis using a gapper and a multi-modulus divider. A frequency synthesizer may comprise a gapper, a multi-modulus divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

Abstract: A memory system having increased throughput is disclosed. Specifically, the memory system includes a first level write combining queue that reduces the number of data transfers between a level one cache and a level two cache. In addition, a second level write merging buffer can further reduce the number of data transfers within the memory system. The first level write combining queue receives data from the level one cache. The second level write merging buffer receives data from the first level write combining queue. The level two cache receives data from both the first level write combining queue and the second level write merging buffer. Specifically, the first level write combining queue combines multiple store transactions from the load store units to associated addresses. In addition, the second level write merging buffer merges data from the first level write combining queue.

Abstract: Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, halt detection logic can initiate a forced halt sequence that causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.

Abstract: Various aspects provide for aggregating a plurality of signals to generate a combined signal. An aggregation component is configured for reformatting a plurality of first signals and combining the plurality of first signals to generate a combined signal that comprises a higher data rate than a data rate associated with the plurality of first signals. A transmitter component is configured for receiving the combined signal and generating one or more data streams based on the combined signal. In an aspect, the aggregation component is additionally configured for reformatting and/or combining the plurality of first signals and at least one second signal to generate the combined signal. In another aspect, a receiver component is configured for generating a pseudo signal at a data rate of the combined signal. In yet another aspect, a de-aggregation component is configured for recovering the plurality of first signals and/or the at least one second signal from the pseudo signal.

Abstract: Various aspects provide for non-intrusively monitoring a network system. A multiplexing component is configured to receive a plurality of first encoded signals and generate a plurality of second encoded signals. The plurality of second encoded signals contain a different data rate and a different number of network lanes than the plurality of first encoded signals. A monitoring component is configured to identify a block location for repeating blocks and an alignment marker in each of the plurality of first encoded signals and/or the plurality of second encoded signals. The monitoring component can also be configured to identify one or more defects, identify error information and/or determine one or more skew values associated with the plurality of first encoded signals and/or the plurality of second encoded signals.

Abstract: In an Optical Transport Network (OTN) system, methods and devices are provided for communicating rate-adaptive OTUk frames. One method determines channel statistics for a fiber span connecting a transmitter to a receiver. A client input data rate is determined that is sufficient to meet a minimum communication threshold, and a rate-adaptive OTUk frame format is determined sufficient to carry the client input data rate. The format comprises a set of (n) allocated slots of client input data in a rate-adaptive OTUk frame comprising (m) slots, where (n) is less than or equal to (m). The method then fills the rate-adaptive OTUk frame, including (m?n) unallocated slots, using one of two processes. The first process fills the rate-adaptive OTUk frame with parity bits computed from client input data. The second process fills at least a portion of the rate-adaptive OTUk frame with and dummy bits.

Abstract: Various aspects provide for implementing a cache coherence protocol. A system comprises at least one processing component and a centralized controller. The at least one processing component comprises a cache controller. The cache controller is configured to manage a cache memory associated with a processor. The centralized controller is configured to communicate with the cache controller based on a power state of the processor.

Abstract: Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor.

Abstract: Cable systems and assemblies integrate a reduced number of twin axial copper pairs to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial copper pairs comprise four or less twin axial copper pairs, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals. A processor can be integrated with the twin axial copper pairs operate to encode the signals for fast transmission speeds.

Abstract: Various aspects provide for facilitating prediction of instruction pipeline hazards in a processor system. A system comprises a fetch component and an execution component. The fetch component is configured for storing a hazard prediction associated with a group of memory access instructions in a buffer associated with branch prediction. The execution component is configured for executing a memory access instruction associated with the group of memory access instructions as a function of the hazard prediction entry. In an aspect, the hazard prediction entry is configured for predicting whether the group of memory access instructions is associated with an instruction pipeline hazard.

Abstract: Various aspects provide a high frequency voltage supply monitor capable of monitoring high frequency variations of the voltage supply inside a microelectronic circuit substantially in real time. The voltage supply monitor can comprise a differential amplifier circuit having a substantially constant gain over a wide bandwidth, allowing the supply voltage variations to be amplified according to a known gain under a wide range of conditions. The amplified signal can then be sent to an output port for monitoring and measurement by an external display device.

Abstract: Various embodiments provide for a system on a chip or a server on a chip that performs flow pinning, where packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor/multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet interface in parallel. Each of the queues can issue interrupts to their assigned processors, allowing each of the processors to receive packets from their respective queues at the same time. Packet processing speed is therefore increased by receiving and processing packets in parallel for different streams.