Abstract: A method is provided for performing chromatic dispersion (CD) pre-compensation. The method generates an electronic signal at a transmitter, and uses a transmit CD compensation estimate to compute a CD pre-compensation filter. The transmit CD pre-compensation filter is used to process the electronic signal, generating a pre-compensated electronic signal. The pre-compensated electronic signal is converted into an optical signal and transmitted to an optical receiver via an optical channel. In one aspect, the transmitter generates a test electronic signal and the CD compensation estimate uses a first dispersion value to compute a first CD compensation filter. The transmitter accepts a residual dispersion estimate of the test optical signal from the first optical receiver CD compensation filter, generated from a (receiver-side) CD estimate, and then the transmit CD estimate can be modified in response to the combination of the first dispersion value and residual dispersion estimate.

Abstract: A method is provided for Single Carrier-Frequency-Division Multiple Access (SC-FDMA) Physical Uplink Control Channel (PUCCH) format 1/1a/1b detection in a wireless communications receiver. The receiver accepts a plurality of multicarrier signals transmitted simultaneously from a plurality of transmitters, with overlapping carrier frequencies. For each multicarrier signal, a single tap measurement of time delay is performed using a Direction of Arrival (DoA) technique. In response to the single tap measurements, PUCCH 1/1a/1b format signals are detected. Prior to performing the single tap measurements, the multicarrier signals are decorrelated in the time domain, using corresponding orthogonal code covers. Subsequent to the single tap measurements, each multicarrier signal is decorrelated in the frequency domain, using a corresponding cyclic shift.

Abstract: System and method for controlling updates of a data structure are disclosed. In one embodiment, the method includes providing a data structure that includes a hierarchically arranged set of nodes and branches, and each node has two or less branches, recording a total number of nodes in the data structure, determining whether to update the data structure according to one or more triggering conditions, generating an updated data structure in response to the one or more triggering conditions, and storing the updated data structure in a memory. The method of recording a total number of nodes includes incrementing a count of the total number of nodes by one when a new node is added to the data structure, and decrementing a count of the total number of nodes by one when a node is removed from the data structure.

Abstract: In a system-on-chip (SoC), a method is provided for partitioning access to resources. A plurality of processors is provided, including a configuration master (CM) processor, a memory, a plurality of OSs, and accessible resources. The method creates a mapping table with a plurality of entries, each entry cross-referencing a range of destination addresses with a domain ID, where each domain ID is associated with a corresponding processor. Access requests to the resource are accepted from the plurality of processors. Each access request includes a domain ID and a destination address. A mapping table is consulted to determine the range of destination addresses associated with the access request domain IDs. The accesses are authorized in response to the access request destination addresses matching the range of destination addresses in the mapping table, and the authorized access requests are sent to the destination addresses of the requested resources.

Abstract: An operating system (OS) is provided including a hardware-based task scheduler, with a method for managing OS sourced tasks to be performed by a central processing unit (CPU). An OS, partially enabled as software instructions stored in a computer-readable medium and executed by the CPU, generates CPU tasks. The CPU tasks are buffered in a computer-readable task database memory. CPU task IDs associated with the buffered CPU tasks are enqueued in a CPU queue. Subsequently, the CPU dequeues a first task ID from the CPU queue, and accessing a first CPU task from the task database associated with the first CPU task ID. The CPU delivers the first CPU task to the OS. The OS generates the CPU instructions needed to perform the first CPU task, and sends the CPU instructions to the CPU for performance.

Abstract: Systems and methods for smoothing jitter generated by byte stuffing. A frequency synthesizer comprises a smoothing logic coupled with a PLL. The smoothing logic is configured to modify a phase error signal generated by a phase frequency detector into a distributed phase error signal that spread over multiple clock cycles. The distributed phase error signal is used to drive a DCO. The smoothing logic may comprise a ramping logic operable to generate a series of ramping values to substitute a phase difference in the phase error signal. The phase difference may correspond to a stuffing byte.

Abstract: A system and method are provided for using feedback to control processor frequencies in a system-on-chip (SoC). The method is associated with an SoC having a processor operating frequency responsive to a processor supply voltage on a first SOC interface, and a controller for managing the operating frequency. The controller accepts a frequency selection command associated with a first operating frequency, at a second SoC interface. The controller sends a first voltage command associated with the first frequency, via a third SOC interface, to a voltage regulator supplying the processor supply voltage. Then, the controller monitors the processor supply voltage. In response to detecting a processor first supply voltage, the processor is enabled to operate at the first frequency.

Abstract: A device (e.g., an integrated circuit memory device such as a static random access memory device) includes word line drivers. Each of the word line drivers includes a pull-up device that is coupled to a node via a shared line. A precharge device is coupled between a power supply and the node. The precharge device and a pull-up device for a selected word line driver are controlled to allow the power supply to charge the node and then to allow the charge stored in the node to flow into a word line corresponding to the selected word line driver.

Abstract: A system and method are provided for resynchronizing a transmission signal using a jitter-attenuated clock derived from an asynchronous gapped clock. A first-in first-out (FIFO) memory accepts an asynchronous gapped clock derived from a first clock having a first frequency. The gapped clock has an average second frequency less than the first frequency. The input serial stream of data is loaded at a rate responsive to the gapped clock. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock, averaged, and an averaged numerator (A and an averaged denominator (AD) are generated. The first frequency is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency. The FIFO memory accepts the jitter-attenuated second clock and supplies data from memory at the second frequency. A framer accepts the data from the FIFO memory and the jitter-attenuated second clock.

Abstract: A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. The outstanding load miss buffer stores a first missed load instruction in a first primary entry. Additional missed load instructions that are dependent on the first missed load instructions are stored in dependent entries of the first primary entry or in shared entries. If a shared entry is used for a missed load instruction the shared entry is associated with the primary entry.

Abstract: A system and method are provided for Single Carrier-Frequency-Division Multiple Access (SC-FDMA) Physical Uplink Control Channel (PUCCH) format 2/2a/2b detection. A receiver accepts a plurality of multicarrier signals transmitted simultaneously from a plurality of transmitters, with overlapping carrier frequencies. For each multicarrier signal, a single tap measurement of time delay is performed using a Direction of Arrival (DoA) technique. After performing a back-end processing operation, PUCCH 2/2a/2b format signals are detected. The back-end processing operation is selected from one of the following options: (1) decorrelation, channel estimation, equalization per user, and decoding per user; (2) channel estimation, equalization, and decoding per user; (3) decorrelation plus maximum likelihood detection (ML) per user; and, (4) ML detection over all users. Selection criteria is also provided.

Abstract: Systems and methods are provided that facilitate cache miss detection in an electronic device. The system contains a probabilistic filter coupled to the processing device. A probing component determines existence of an entry associated with a request. The probing component can communicate a miss token without the need to query a cache. Accordingly, power consumption can be reduced and electronic devices can be more efficient.

Abstract: Systems and methods are provided that facilitate power management in a processing device. The system contains a power management component and a coupled to the processing device. The power management component determines and input rate and target voltages and/or frequency. The power management component can scale voltages and/or frequencies based on target voltages and/or frequencies. Accordingly, power consumption can be reduced and processing devices can be more efficient.

Abstract: Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, a forced halt sequence can be initiated, which causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.

Abstract: Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, halt detection logic can initiate a forced halt sequence that causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.

Abstract: Systems and methods for generating gapped signals comprising a Delta Sigma Modulator (DSM) configured to generate gapping control signals used to control gap removal rates of an associated gapping unit. The DSM is configured to generate a gapping control signal based on a value of an overflow resulted from performing adding a first number with a remainder of a stored value modulo a second number. The gap removal rates as well as the gap removal resolutions can be adjusted by selecting appropriate values of the first number, the stored value, and the second number. The gapping resolution can be a portion of a pulse. The first number and the second number may be derived from an intended frequency ratio between a gapped signal and a corresponding input signal. The gapping unit may comprise a gapping circuit or a multi-modulus divider.

Abstract: Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

Abstract: Various aspects provide for implementing a cache coherence protocol. A system comprises at least one processing component and a centralized controller. The at least one processing component comprises a cache controller. The cache controller is configured to manage a cache memory associated with a processor. The centralized controller is configured to communicate with the cache controller based on a power state of the processor.

Abstract: A system and method are provided for the cut-through encryption of packets transmitted via a plurality of input/output (IO) ports. A system-on-chip is provided with a first plurality of input first-in first out (FIFO) memories, an encryption processor, and a first plurality of output FIFOs, each associated with a corresponding input FIFO. Also provided is a first plurality of IO ports, each associated with a corresponding output FIFO. At a tail of each input FIFO, packets from the SoC are accepted at a corresponding input data rate. Packet blocks are supplied to the encryption processor, from a head of each input FIFO, in a cut-through manner. The encryption processor supplies encrypted packet blocks to a tail of corresponding output FIFOs. The encrypted packet blocks are transmitted from each output FIFO, via a corresponding IO port at a port speed rate effectively equal to the corresponding input data rate.

Abstract: A method is provided for process, voltage, temperature (PVT) stable transfer function calibration in a differential amplifier. The gain resistors of a differential amplifier are initially selected to achieve a flat amplitude transfer function in the first frequency band. After calibration, the degeneration capacitor is connected and tuned until a peaked amplitude transfer function is measured, which is resistant to variations in PVT. As an alternative, the degeneration capacitor is not disconnected during initial calibration. Then, the gain resistors and the degeneration capacitor values are selectively adjusted until the first peaked amplitude transfer function is obtained. The peaked amplitude transfer function remains even more stable to variations in PVT than the flat amplitude calibration method.