Abstract: One or more processing units confirm existence of narrow band interference in a signal by using an estimate f of the frequency, to check for one or more harmonics. In illustrative embodiments, the estimate f is automatically identified as a second harmonic if a predetermined criterion is satisfied by the signal (in the frequency domain) at either of two frequencies namely (A) frequency f/2 and (B) frequency (M?f)/2 and whichever of these two frequencies is stronger is identified as the fundamental frequency. In several such embodiments, the estimate f is automatically identified as a third harmonic if a predetermined criterion is satisfied by the signal (in the frequency domain) at any of three frequencies namely (C) frequency f/3 and (D) frequency (M?t)/3 and (E) frequency (M+f)/3. If the predetermined criteria are not met at all five frequencies (A)-(E) then f is identified as the fundamental frequency.

Abstract: A multistage latch-based isolation cell is provided. The isolation cell includes a latch to receive a first binary signal and an enable signal. The latch initially supplies a second binary signal with an unknown value in response to the enable port receiving an enable signal having a first polarity value, and subsequent to receiving the first binary signal with a first value, supplying the second binary signal with the first value. The isolation cell includes a delay device to receive the enable signal and to supply a delayed enable signal. A reset latch receives the second binary signal, the delayed enable signal, and a reset pulse. The reset latch supplies a third binary signal equal to the first value in response to the reset latch receiving the reset pulse, followed by the delayed enable signal with the first polarity value, followed by the second binary signal.

Abstract: A system and method are provided for converting multichannel serial data streams into packets. The method accepts a plurality of serial data streams in a corresponding plurality of channels. In a time domain multiplexed (TDM) fashion, groups with an undetermined number of data bits are packed from each data stream, into an associated channel segment queue, where each segment includes a predetermined number of bits. In a TDM fashion, segments are loaded into an associated channel payload queue, where each payload includes a predetermined number of segments. Once a payload is filled, an associated pointer is created in a pointer queue. The method selects a pointer from the pointer queue, creates a packet from the payload associated with the selected pointer, and transmits the packet via a packet interface. The packet overhead may include information stored in the pointer, a packet header, or a cyclic redundancy check (CRC) checksum.

Abstract: A system is provided for generating an output clock used for N.5 modulus division. An edge-slip circuit accepts a modulus count, a divisor select signal, and a clock signal having a frequency greater than a modulus count frequency. The edge-slip circuit also has an input to accept an output clock signal, and an output to supply a clock slip signal (NE). An exclusive-or (XOR) has an input to accept a buffered clock signal (NF) and the clock slip signal (NE). The XOR has an output to supply the output clock signal. The output clock signal has a frequency equal to a buffered clock signal frequency, with no skipped clock edges, when the clock slip signal does not change logic levels. Alternatively, the output clock signal frequency is equal to the buffered clock signal frequency, with a skipped clock edge, when the clock slip signal changes logic levels.

Abstract: A system and method are provided for synthesizing signal frequencies using a single reference clock and a primitive ratio of integers. The method accepts a plurality (k) of reference frequency values (fri), where 1?i?k, associated with a corresponding plurality of synthesized frequency values (foi). For each synthesized frequency value, a raw ratio of integers Nprawi and Dprawi is calculated, such that: f o i = Np raw i Dp raw i × f r i . A greatest common divisor (GCD) of Nprawi and Dprawi and a primitive ratio of integers Np i Dp i is found for each raw ratio of integers, such that: N p i = Np raw i GCD ? ( Np raw i , Dp raw i ) ; and , ? D p i = Dp raw i GCD ? ( Np raw i , Dp raw i ) .

Abstract: A system and method are presented for providing packet and time division multiplex (TDM) services in a data communication interface. The method accepts packets at a first rate over a packet interface, and transfers time-sensitive data in the packets as packet data units (PDUs) having a smaller number of bits than a packet and a second rate, faster than the first rate. The method transforms the PDUs into frames in a first TDM protocol. Typically, the PDUs are transformed into units having a smaller number of bits than the PDU and a third rate, faster than the second rate. Then, the TDM frames are transmitted over a line interface.

Abstract: A circuit analysis tool is provided for optimizing circuit clock operating frequency using useful skew timing analysis. The instructions supply clock signal with an optimized operating frequency. A first gate signal input slack time is determined with respect to the clock signal to the first gate. If the first gate signal input has a negative slack time, a delay is added to the first clock signal. A second gate signal input slack time is determined with respect to the clock signal to the second gate. If the second gate signal input slack time is negative, a delay is added to the second clock signal necessary to create a second gate signal input positive slack time. In response to the first and second gate signal input positive slack times, it is determined that the circuit successfully operates at the clock optimized operating frequency.

Abstract: A method is provided for process, voltage, temperature (PVT) stable transfer function calibration in a differential amplifier. The gain resistors of a differential amplifier are initially selected to achieve a flat amplitude transfer function in the first frequency band. After calibration, the degeneration capacitor is connected and tuned until a peaked amplitude transfer function is measured, which is resistant to variations in PVT. As an alternative, the degeneration capacitor is not disconnected during initial calibration. Then, the gain resistors and the degeneration capacitor values are selectively adjusted until the first peaked amplitude transfer function is obtained. The peaked amplitude transfer function remains even more stable to variations in PVT than the flat amplitude calibration method.

Abstract: One or more processing units are programmed to select from among M tones in a frequency domain representation of a signal, a set of tones including at least a strongest tone (relative to background noise) and a tone adjacent thereto. From among M complex numbers in the frequency domain representation of the signal, a set of complex numbers are identified and denoted as a vector Z, corresponding to the selected set of tones. Vector Z is then multiplied with each of M columns of a matrix G which is predetermined to identify a sub-resolution maxima in Z. The M products that result from the vector multiplication of Z and G are used to determine and store in memory at least one or both of: (A) a flag indicating presence or absence of narrowband interference in the signal; and (B) an estimate of a frequency of the narrowband interference.

Abstract: A system and method are provided for in-situ inspection optical inspection during a parallel polishing process. The method provides a polishing device with a spindle bit for holding a metallurgical sample, and a rotatable wheel having an inner diameter with a top surface for accepting a polishing compound and a transparent outer diameter. An optical system underlies the wheel outer diameter for recording images of the metallurgical sample. The method polishes the metallurgical sample against the wheel inner diameter. Without releasing the metallurgical sample from the spindle bit, the metallurgical sample is moved to a first position overlying the wheel outer diameter, and the metallurgical sample is optically inspected. In one aspect, the polishing device has a cleaning system overlying the wheel outer diameter, and the method sprays the wheel outer diameter with cleaning solution to support an in-situ inspection.

Abstract: A latch device is provided with a relay and a shadow latch. The relay has an input to accept a binary relay input signal, an input to accept a clock signal, an input to accept a shadow-Q signal, and an output to supply a binary Q signal value equal to the relay input signal value. The relay output is supplied in response to the relay input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the relay input signal, an input to accept the clock signal, and an output to supply the shadow-Q signal with a value equal to an inverted Q signal value. The shadow latch output is supplied in response to the relay input signal and clock signal.

Abstract: A system and method are provided for stacking storage drives in a network attached storage (NAS) system. The method provides a NAS stacking network including at least a first and second stackable building block (SBB), where each SBB includes a head, with an embedded processor and storage application, and a storage drive including client files. The method connects a first interface of the first SBB to a client computer device via a LAN switch, and connects a second interface of the first SBB to the first interface of the second SBB. A directory is built of client files stored in the first and second SBBs. The directory is maintained in both the first and second SBBs. In one aspect, the first SBB, acting as a primary SBB, provides access to NAS stacking network directory structure in response to an inquiry from a client computer connected to the LAN switch.

Abstract: A method is provided for assembling a stack of surface-mount devices (SMDs) on a substrate. The method provides a substrate, die, or printed circuit board (PCB) with a top surface having a landing pad and a first reference feature. An alignment jig is placed overlying the substrate top surface. The alignment jig second reference feature is aligned with respect to the substrate first reference feature. A first SMD is placed overlying the substrate landing pad. The first SMD third reference feature is aligned with respect to the alignment jig second reference feature. A second SMD is placed overlying the substrate top surface. Then, the alignment jig first boundary feature is mated with the second SMD second boundary feature. In response to the mating, the second SMD first interface is aligned over an underlying SMD active element.

Abstract: A system and method provide both inline services and in-network services for a dual-connect service box interposed between a modem and a router. The method transceives communications between a service box wide area network (WAN) port and a local area network (LAN) port of a WAN-connected broadband modem, and between a service box WAN-proxy port and a WAN port of a router. The method also selectively transceives communications between the service box WAN port and a LAN port. A service box binding module monitors messages transceived between the router and the modem to determine the service box WAN IP address, and registers at least one service box WAN IP addresses with a WAN network-connected account server. The method selectively transceives communications in response to an authentification means, which may be identifying an authorized port number in the communications, or identifying an authorized command in the communications.

Abstract: A method is provided for first order accumulation in a single clock cycle. The method accepts a limited gain value and an accumulated value stored in a previous clock cycle. Using combinational logic, the limited gain value is summed with the accumulated value. If the summed value is between upper and lower limits, a non-weighted correction signal is supplied, and the summed value is the storage value. If the summed value is greater than the upper limit, a positive weighting is supplied, the (upper limit+1) is subtracted from the summed value, and the result is the storage value. If the summed value is less than the lower limit, then a negative weighting is supplied, the lower limit is subtracted from the summed value, and the result is the storage value. The storage value is loaded in memory for use as the accumulated value in the subsequent clock cycle.

Abstract: A method is provided for synthesizing signal frequencies using low resolution rational division decomposition in a frequency synthesis device. An integer numerator (n) and an integer denominator (d) ratio is reduced; n/d=IO(NO/DO)=IO+NO/DO=(IO+1)?(DO?NO)/DO, and where NO/DO<1 and NO and DO are integers. NO is reduced; NO=In(Nn/Dn)=In+Nn/Dn=(In+1)?(Dn?Nn)/Dn, where In, Nn, and Dn are integers, and Nn/Dn<1. In, Nn, and Dn are used to create a final numerator divisor. DO is reduced; DO=Id(Nd/Dd)=Id+Nd/Dd=(Id+1)?(Dd?Nd)/Dd, where Id, Nd, and Dd are integers, and Nd/Dd<1. Id, Nd, and Dd are used to create a final denominator divisor. Finally, IO, the final numerator divisor, and the final denominator divisor are used to create a final divisor.

Abstract: A circuit and method perform adaptive spectral enhancement at a frequency ?1 (also called “fundamental” frequency) on an input signal y which includes electromagnetic interference (EMI) at an unknown frequency, to generate a fundamental-enhanced signal ?1 (or its complement). The fundamental-enhanced signal ?1 (or complement) is thereafter used in a notching circuit (also called “fundamental notching” circuit) to generate a fundamental-notched signal y??1. The fundamental-notched signal y??1 is itself enhanced to generate a harmonic-enhanced signal ?2 that is used to notch the fundamental-notched signal y??1 again, in one or more additional notching circuits that are connected in series with the fundamental notching circuit. The result (“cascaded-harmonic-notched” signal) is relatively free of EMI noise (fundamental and harmonics), and is used as an error signal for an adaptation circuit that in turn identifies the fundamental frequency ?1.

Abstract: An optical multi-chip module (MCM) is provided. A printed circuit board (PCB) overlies a package bottom and has die contact regions, each having at least one electrical interface. A first die contact region is formed in a PCB top surface recess, and an optical component die has a bottom surface with an area about matching the PCB top surface recess. The optical component die has an optical port with microlens. An electrical component die has a bottom surface with at least one electrical interface connected to the second die electrical interface, which is connected to the first die electrical interface via a PCB trace. A wire bond is connected between the electrical component die and a package interconnection lead. A cover assembly connector has an optical port with a microlens, configured to communicate with the optical component die optical port, and a fiber port to accept an optical fiber.

Abstract: A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q<1 (decimal). The numerator (p) and the denominator (q) are supplied to a flexible accumulator module, and a divisor is generated as a result. N is summed with a k-bit quotient to create the divisor. In a phase-locked loop (PLL), the divisor and the reference signal are used to generate a synthesized signal having a frequency equal to the synthesized frequency value.

Abstract: A system and method are provided for using a system-on-chip (SoC) memory speed control logic core to control memory maintenance and access parameters. A SoC is provided with an internal hardware-enabled memory speed control logic (MSCL) core. An array of SoC memory control parameter registers is accessed and a set of parameters is selected from one of the registers. The selected set of parameters is delivered to a SoC memory controller, to replace an initial set of parameters, and the memory controller manages an off-SoC memory using the delivered set of parameters.