Abstract: Systems and methods for Phase-Locked Loop (PLL) based frequency synthesizer comprising a dynamic fraction divider in a feedback loop. The dynamic fraction divider employs a dynamic divide ratio that dynamically changes with the jitters and noise spurs contained in an input signal to the PLL, and generates a feedback signal used to adjust the PLL output frequency. The dynamic divide ratio may be determined by comparing the phases of the PLL output signal and the input signal.

Abstract: A system and method are provided for synchronizing a programmable timer time base and external time signal. The method either accepts or supplies an external time signal (e.g., IEEE 1588) at an external interface, links a synchronized time base to the external time signal, and clocks a channel time base with the synchronized time base. Then, a timer channel can be used to perform programmable timer functions in response to the channel time base. Some programmable timer functions include input capture, output compare, quadrature decoding, pulse measurement, frequency measurement, and pulse width modulation (PWM) functions, in one aspect, accepting the external time signal at the external interface includes detecting a packet with a time value, in another aspect, the method uses the channel to detect an event at a channel external interface, and compares the channel time base counter value with an expected value to modify the synchronized time base.

Abstract: A system and method are provided for residence time calculations in a network communications local device. A network interface module in the local device receives a first packet from a network-connected remote device. A timing module in the local device records an arrival time of the first packet with respect to a local reference clock. The timing module tracks adjustments in the local reference clock and records a known departure time, with respect to the local reference clock, of when the first packet will be transmitted from the network interface. The timing module adds a residence time field to the first packet representing the difference between the arrival and departure times, taking into account adjustments in the local reference clock.

Abstract: A system and method are provided for Soft Interference Cancellation (SIC) in receiving Single Carrier Frequency Division Multiple Access (SC-FDMA) Multiple-Input Multiple Output (MIMO) signals. A receiver with Mr antennas accepts multicarrier signals transmitted simultaneously, with N overlapping carrier frequencies. The receiver removes a cyclic prefix (CP), and fast Fourier transforms (FFT) the multicarrier signal from each antenna, supplying Mr number of N-tone signals y. Using either parallel SIC (P-SIC) or successive SIC (S-SIC), interference is canceled in each of the Mr signals, and soft symbols are supplied for each of U layers. Interference is canceled using the P-SIC process by parallel processing the U layers in an i-th iteration, in response to feedback from an (i?1)th iteration. Alternatively, interference is canceled using the S-SIC process by sequentially processing the U layers in an i-th iteration, in the order of u0,u1, . . . , uU?1, using feedback generated from previously processed layers.

Abstract: A system and method are provided for generating a jitter-attenuated clock using an asynchronous gapped clock source. The method accepts a first reference clock having a first frequency. Using the first reference clock, an asynchronous gapped clock is generated having an average second frequency less than the first frequency. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock. Then, DN and DD are averaged. In response to the averaging, an averaged numerator (AN) and an averaged denominator (AD) are generated. Finally, the first frequency (first reference clock) is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency.

Abstract: A circuit and method form a codeword including parity and message bits, as follows. Each codeword has a first part in a current sequence (e.g. a current OTN-row) that is to be now transmitted and second part spread across multiple past sequences (e.g. previously prepared and transmitted OTN-rows). The codewords are grouped into multiple groups such that each codeword within a group has no bit in common with another codeword in that group. Moreover, each codeword has a bit in common with a different codeword in a different group.

Abstract: In a communication device using a plurality of signal enhancement mechanisms, a system and method are provided for managing signal processing power consumption. A receiver accepts a communications signal and analyzes signal integrity. In response to analyzing the signal integrity, a signal enhancement mechanism is changed, and device power consumption is modified in response to changing the signal enhancement mechanism. In one aspect, the receiver changes a receiver signal enhancement mechanism, and modifies its power consumption. For example, one or more of the following receiver signal enhancement mechanisms may be selected: forward error correction (FEC), equalization, dc voltage level, and physical coding sublayer (PCS).

Abstract: A system and method are provided for transmitting and receiving asynchronous channels of information via a SerDes Frame Interface (SFI) 4.2 interface. The SerDes device accepts a plurality of channels operating at asynchronous channel clock rates. Bytes of data from each channel are loaded into a source at the channel clock rates. Once loaded, the bytes of data for each channel are drained from the source at a line clock rate and interleaved into four 64-bit segments. A 2-bit control word is added to each segment, creating 66/64-bit data blocks. The control word indicates the validity of bytes of data within the 66/64-bit data blocks. Then, the 66/64 bit data blocks are transmitted via a SFI4.2 interface in four lanes, at a rate proportional to the line clock rate.

Abstract: Methods and systems for multi-input IIR filters with error feedback are disclosed. By using multiple-inputs to generate multiple outputs during each iteration, a multi-input IIR filter in accordance with the present invention has greatly increased throughput. Furthermore, the addition of a multi-variable error feedback unit in accordance with the present invention in a multiple-input IIR filter can greatly increase the accuracy of the multi-variable IIR Filter.

Abstract: A method and system are provided for accelerated data uploading to a remote service device destination. An on-line (third party) storage device receives an upload request message from a network-connected client device. A unique first descriptor in a descriptor field of the upload request message is accessed and compared to a list of descriptors maintained by the on-line storage device. If the accessed first descriptor is on the list, a first file is read that is stored in the on-line storage device and associated with the accessed first descriptor. The first file is then sent to a network-connected remote service device.

Abstract: A system and method are provided for using queue status to manage power in a system-on-chip (SoC). Messages to be processed are accepted in an SoC with a plurality of selectively enabled processors, and queued. The message traffic can be from an external source via an input/output (IO) interface, or intra-SoC messages between processors. The number of queued messages is monitored and, in response to the number of queued messages exceeding a subscription threshold, one or more processors are enabled. Then, the queued messages are distributed to the enabled processors. Enabling a processor is defined by an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions. Likewise, processors can be disabled in response to the number of queued messages falling below the subscription threshold.

Abstract: An input signal that includes narrowband interference is spectrally enhanced by an adaptive circuit that supplies as output signal(s), portion(s) of NBI at one or more frequencies that change adaptively. The output signal(s) are used in one or more tone predictor(s) to generate, based on prior values of the NBI portion, one or more predicted tone signals that are subtracted from a received signal containing the NBI, and the result is used in the normal manner, e.g. decoded. The adaptive circuit and the one or more tone predictor(s), form a feed-forward NBI predictor wherein the received signal is supplied as the input signal of the adaptive circuit. The result of subtraction may be supplied to a slicer that slices the result, yielding a sliced signal which is subtracted from the received signal to generate a signal can be used as the input signal, to implement a feedback NBI predictor.

Abstract: A system and method are provided for a system-on-chip (SoC) management module to monitor and dynamically control processor core operating voltages. An SoC is provided with a plurality of processor cores, a plurality of voltage regulators, an internal management module, and at least one temperature sensor. The management module compares monitored temperatures to threshold values, and in response generates voltage commands. The management module sends the voltage commands to the voltage regulators. Each voltage regulator adjusts the operating voltage supplied to a corresponding processor core in response to the voltage commands.

Abstract: A method is provided for process, voltage, temperature (PVT) stable transfer function calibration in a differential amplifier. The gain resistors of a differential amplifier are initially selected to achieve a flat amplitude transfer function in the first frequency band. After calibration, the degeneration capacitor is connected and tuned until a peaked amplitude transfer function is measured, which is resistant to variations in PVT. As an alternative, the degeneration capacitor is not disconnected during initial calibration. Then, the gain resistors and the degeneration capacitor values are selectively adjusted until the first peaked amplitude transfer function is obtained. The peaked amplitude transfer function remains even more stable to variations in PVT than the flat amplitude calibration method.

Abstract: A latch device is provided with a driver and a shadow latch. The driver has an input to accept a binary driver input signal, an input to accept a clock signal, and an input to accept a shadow-Q signal. The driver has an output to supply a binary Q signal equal to the inverse of the driver input signal, in response to the driver input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the driver input signal, and an input to accept the clock signal. The shadow latch has an output to supply the shadow-Q signal equal to the inverted Q signal, in response to the driver input signal and clock signal.

Abstract: A system and method are provided for downloading data to a client device by deferral to an on-line storage device. A client sends a login request to a network-connected remote service device, and receives a remote service identification (ID) from the remote service device. The client sends a token request message, with the remote service ID, to a network-connected on-line storage device, and receives a first token identification (ID) associated with a first session and an on-line storage ID from the on-line storage device. The client sends an upload request message to the remote service device. The upload request message includes the first token ID and on-line storage ID, and identifies a first file to be uploaded to the on-line storage device. Subsequent to the on-line storage device receiving the first file from the remote service device, the client downloads the first file from the on-line storage device.

Abstract: Disclosed herein is a pseudo single-phase flip-flop. The master section includes a pre-dissipation stage and a first keeper. The pre-dissipation stage discharges the first keeper to the mDb second binary value, and selectively charges the first keeper with the mDb first binary value in the master pass mode. The pre-dissipation stage selectively prevents the first keeper from charging to the mDb first binary value in response to one of the clock phases. The slave section includes a pre-charge stage, a second keeper, a post-dissipation stage, and a third keeper. The second keeper maintains a first binary value in a slave pass mode when the mDb signal has a second binary value. The second keeper supports the second binary value in the slave pass mode when the mDb signal has the first binary value. The third keeper maintains the Q signal binary value during the slave hold mode.

Abstract: A system and method are provided for using a system-on-chip (SoC) memory manager to dynamically shutdown and restart an off-chip memory module. After determining that a memory switch is to be enacted, an SoC memory switching core asserts a hold on processor operations. The memory switching core transfers data from a source memory module to a destination memory module. In a shutdown operation, data is transferred from a first memory module source to an external second memory module destination interfaced to the memory switching core. In a restart operation, data is transferred from the second memory module source to the first memory module destination. The memory switching core uses a memory map for translating the data addresses in the source memory module to data addresses in the destination memory module. Then, the memory switching core deasserts the hold on processor operations.

Abstract: A system and method are provided for automatically converting a hardware abstraction language representation of a single-channel hardware module into a hardware abstraction language representation of a multi-channel module. Initially, a hardware abstraction language representation of a single channel hardware module is provided having an input port, output port, and a register. The method defines a number of channels and establishes a context switching memory. Commands are created for intercepting register communications. Commands are also created for storing the intercepted communications in a context switching memory, cross-referenced to channel. The module is operated using the created commands and stored communications from the context switching memory.

Abstract: A system and method are provided for framing messages in a data streams encoded with redundant information for transmission and recovering the messages at a receiver. The transmission method accepts an energy waveform representing N words at a first bit rate, encoded with redundant information, where each word includes P number of bits. The N words are transformed, creating N transcoded words, where each transcoded word includes Q number of bits, and where Q<P. The N transcoded words are mapped into M lanes in a buffer memory, where M>1 and each lane receives a frame of N/M transcoded words. A frame alignment marker is generated and mapped into each frame. Each frame is represented as an energy waveform that is transmitted on a corresponding physical lane at the first bit rate divided by M.