Abstract: Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

Abstract: Various aspects provide large receive offload (LRO) functionality for a system on chip (SoC). A classifier engine is configured to classify one or more network packets received from a data stream as one or more network segments. A first memory is configured to store one or more packet headers associated with the one or more network segments. At least one processor is configured to receive the one or more packet headers and generate a single packet header for the one or more network segments in response to a determination that a gather buffer that stores packet data for the one or more network segments has reached a predetermined size.

Abstract: Various aspects of the present disclosure provide for a system that is able to boot from a variety of media that can be connected to the system, including SPI NOR and SPI NAND memory, universal serial bus (“USB”) devices, and devices attached via PCIe and Ethernet interfaces. When the system is powered on, the system processor is held in a reset mode, while a microcontroller in the system identifies an external device to be booted, and then copies a portion of boot code from the external device to an on-chip memory. The microcontroller can then direct the reset vector to the boot code in the on-chip memory and brings the system processor out of reset. The system processor can execute the boot code in-place on the on-chip memory, which initiates the system memory and the second stage boot loader.

Abstract: Techniques for multiplexing and demultiplexing signals for optical transport networks are presented. A network component comprises a multiplexer component that multiplexes a plurality of signals having a first signal format to produce a multiplexed signal in accordance with a second signal format, while maintaining error correction code (ECC) of such signals and without decoding such signals and associated ECC. The multiplexer component interleaves the plurality of signals with stuffing and adds overhead without generating new ECC. A second network component receives the multiplexed signal as part of a frame in accordance with the second signal format. A demultiplexer component of the second network component demultiplexes the multiplexed signal using the original ECC associated with the plurality of signals, wherein the second network element removes and filters the stuffing from the multiplexed signal and produces a plurality of demultiplexed signals as an output, in accordance with the first signal format.

Abstract: A system and method are provided for using a system-on-chip (SoC) memory manager to optimize the use of off-chip memory modules. A SoC memory controller receives a request for a first data block, subsequent to shutting the first memory down, and determines that the first data block is stored in the first memory. A SoC memory switching core uses a memory map to translate the first data block address in the first memory module to a first data block address in the second memory module. If the first data block is present in an on-SoC cache, the first data block is supplied on the SoC data bus from the cache. Then, the cache is loaded with a plurality of data blocks from a corresponding plurality of addresses in the second memory module, associated with the first data block address.

Abstract: A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single cache access and stores the data in the load miss result buffer. When missed load instructions are reissued from the outstanding load miss buffer, data for the missed load instructions are read from the load miss result buffer rather than the level one cache. Because the data is stored in the load miss result buffer, other instructions that may change the data in level one cache do not cause data hazards with the missed load instructions.

Abstract: The described systems and methods can facilitate efficient and effective information storage. In one embodiment a system includes a hash component, a queue request order component and a request queue component. The hash component is operable to hash a request indication. The queue request order component is operable to track a queue request order. The request queue component is operable to queue and forward requests in accordance with direction from the queue request order component. In one embodiment, the storage component maintains a request without stalling a request in an aliasing condition.

Abstract: A photodetector with a bandwidth-tuned cell structure is provided. The photodetector is fabricated from a semiconductor substrate that is heavily doped with a first dopant. A plurality of adjoining cavities is formed in the semiconductor substrate having shared cell walls. A semiconductor well is formed in each cavity, moderately doped with a second dopant opposite in polarity to the first dopant. A layer of oxide is grown overlying the semiconductor wells and an annealing process is performed. Then, metal pillars are formed that extend into each semiconductor well having a central axis aligned with an optical path. A first electrode is connected to the metal pillar of each cell, and a second electrode connected to the semiconductor substrate. The capacitance between the first and second electrodes decreases in response to forming an increased number of semiconductor wells with a reduced diameter, and forming metal pillars with a reduced diameter.

Abstract: A system and process are provided for managing bandwidth in a network-attached storage (NAS) system. The process provides a NAS storage device having a network interface, at least one storage drive, a controller head, and a NAS bandwidth manager application enabled as software instructions. The process receives a request for access to a file system share from a client via a network having a maximum throughput rate. The NAS bandwidth manager identifies the client and provides client access to the NAS at an allocated bandwidth. In one aspect, the NAS bandwidth manager consults a preconfigured bandwidth allocation chart in response to the client request. In another aspect, the NAS bandwidth manager may receive a request for a particular bandwidth from the client.

Abstract: A load/store unit with an outstanding load miss buffer and a load miss result buffer is configured to read data from a memory system having a level one cache. Missed load instructions are stored in the outstanding load miss buffer. The load/store unit retrieves data for multiple dependent missed load instructions using a single memory access and stores the data in the load miss result buffer. The load miss result buffer includes dependent data lines, dependent data selection circuits, shared data lines and shared data selection circuits. The dependent data selection circuits are configured to select a subset of data from the memory system for storing in an associated dependent data line. Similarly, the shared data selection circuits are configured to select a subset of data from the memory system for storing in an associated shared data line.

Abstract: A method is provided for performing chromatic dispersion (CD) compensation. A zero-forcing filter is calculated with a number of taps (n) required to nullify a chromatic dispersion frequency response of an optical channel. The number of taps in the zero-forcing filter is truncated to a number equal to (n?x), where x is an integer greater than 0. In one aspect, the chromatic dispersion frequency response of the optical channel is partitioned into a plurality of constituent chromatic dispersion responses, and a zero-forcing filter is calculated for each of the plurality of constituent chromatic dispersion responses. The number of taps in each of the plurality of zero-forcing filters is truncated, and the CD compensation filter is formed for each of the plurality of truncated tap zero-forcing filters. In another aspect, the tap values of the zero-forcing filter are quantized to a finite quantization set.

Abstract: A system and method are provided for using a thermal management core to control temperature on a system-on-chip (SoC). The method provides an SoC with an internal thermal management core and an internal temperature sensor. For example, the sensor may be located on or near a processor core die. The thermal management core monitors temperatures recorded by the SoC temperature sensor, and sends commands for controlling SoC device functions. In response to these commands, the thermal management core monitors a change in the temperature at SoC temperature sensor. The temperature sensor may be monitored via a dedicated SoC internal interface connecting the processor and the thermal management core. Alternately, the thermal management core may poll for temperatures via a system management bus (SMBUS) SoC external interface connecting the processor and thermal management core. Further, a dedicated SoC external alert interface connecting the processor and thermal management core may be monitored.

Abstract: A system and method have been provided for passively isolating a latch circuit. The method provides a latch having a first input, an output, and a reset port. The latch first input is selectively connected to a first reference voltage. While the latch first input is connected to the first reference voltage, the latch is reset. Subsequent to disconnecting the latch first input from the first reference voltage, a first node is selectively connecting to the latch first input. In response to selectively connecting the first node, a first analog signal is supplied to the latch first input. Subsequent to resetting the latch, the first analog signal is captured and the latch output supplies a digital signal responsive to the captured first analog signal.

Abstract: Various aspects provide for a hardware SATA virtualization system without the need for backend and frontend drivers and native device drivers. A lightweight SATA virtualization handler can run on a specialized co-processor and manage requests enqueued by individual VMs. The lightweight SATA virtualization handler can also perform the scheduling of the requests based on performance optimizations to reduce seek time as well as based on the priority of the requests. The specialized co-processor can communicate to an integrated SATA controller through an advanced host controller interface (“AHCI”) data structure that is built by the system processor and has commands from one or more VMs.

Abstract: A power supply source selection circuit is provided with a comparator and a switch. The comparator has an input to accept a first reference voltage directly proportional to a bandgap reference voltage. For example, the bandgap voltage may be derived from a battery voltage. The comparator has an input to accept a second reference voltage directly proportional to a first supply voltage (e.g., a line voltage), and an output to supply a switch signal in response to comparing the second reference voltage to the first reference voltage. The switch has an input to accept the first supply voltage, an input to accept a second supply voltage, and input to accept the switch signal. The switch has an output to supply a third supply voltage to a regulator. The third voltage has a voltage potential less than or equal to a maximum voltage value. The switch selects between the first supply voltage and the second supply voltage in response to the switch signal.

Abstract: A pattern method is provided for testing an optical lens. The method provides a lens for test, including a first lens surface with a focal plane in object space and a second lens surface with a focal plane in image space. Also provided is a pattern test fixture including an imaging device and a target pattern. The lens is positioned so that the imaging device is located outside the object space focal plane and the target pattern located is outside the image space focal plane. The imaging device, such as a microscope, magnification device, human eye, or camera, is used to view the target pattern. A viewed image representation of the target pattern is received in the imaging device and compared to the target pattern. More typically, the viewed image representation is compared to a target pattern copy.

Abstract: Circuit and method for resetting clock circuitry. The circuit includes a chain of cascading units, each of which receives an input of a number of parallel bit streams and outputs a different number of parallel bit streams. A chain of dividers provides one or more divided clock signals to the cascading units, wherein the divided clock signals are based on a gated common clock signal. An asynchronous reset signal is delivered to the dividers, and when asserted sets the dividers to a reset state. A clock source provides an ungated common clock signal. A clock gating circuit generates the gated common clock signal based on the ungated common clock signal, and is configured to hold the gated common clock signal while the asynchronous reset signal is asserted. The clock gating circuit provides the gated common clock signal to the dividers when the asynchronous reset signal is de-asserted.

Abstract: A method is provided for forwarding packets. Using a control plane state machine, addresses in a packet header are examined to derive a pointer value. The pointer value is used to access entries in a result database to identify routing information, a buffer pool ID associated with a location in memory, and a queue ID. A direct memory access (DMA) engine writes the packet into the memory location in response to the first message including the buffer pool ID. The QM prepares a second message associated with the packet, the second message including the routing information, the memory allocation in the buffer pool ID, and the queue ID. An operating system reads the second message, reads the packet from the memory allocation, modifies the packet header using the routing information, and writes the modified packet back into the memory allocation.

Abstract: Providing for improved write processes of a semiconductor memory are disclosed herein. By way of example, a programmable write assist can be provided that includes partially discharging a supply voltage applied to a memory cell. Partially discharging the supply voltage can improve write speeds to the memory cell, as well as improve reliability of the write process. A write assist circuit can cause the discharging in response to a resistance-modulated signal. Moreover, the resistance-modulated signal can be configured to control an amount or speed of the discharging of the supply voltage. Further, modulation control can be provided to mitigate discharging of the supply voltage beyond a target level, to reduce data loss in a target data cell or an adjacent data cell.

Abstract: A circuit analysis tool is provided for die size reduction analysis. A processor determines a first initial output slack time. If the first initial output slack time is greater than zero, a first circuit element is modeled with a second die area, less than the first die area. The second die area is associated with a third delay greater than the first delay. Then, the second data signal is modeled equal to the first data signal with the third delay. If a first modified output slack time is greater than or equal to zero, the first circuit element first die can be replaced with the second die. If the first modified output slack time is a first value less than zero, a first delay is added to the clock signal that is greater than or equal to the first value.