Abstract: Resistive switching memory architectures disclosed herein are capable of achieving fast read/write times and, particularly in the case of multi-bank parallel processing, executing many read or write operations per second. Because resistive switching memory is not guaranteed to be error free, resistive memory controllers can be programmed for error management when paired with such memory architectures. To reduce error management overhead, a dedicated error pin is provided to mitigate or avoid the need for a status read in conjunction with each read or write operation issued to a memory device. A status read can be implemented in response to an error signal on the dedicated error pin, but otherwise can be avoided.

Abstract: Providing for an electronic memory apparatus having high-density, non-volatile memory arrays in conjunction with a high-speed communication interface is disclosed herein. In some embodiments, the electronic memory apparatus can include multiple banks of two-terminal memory, communicatively connected to a modified dynamic random access memory bus and configured to operate according to a modified communication protocol. In one or more embodiments, the high-speed communication interface can comprise more than ten command and address pins to identify individual memory banks (or subsets of memory banks) of the multiple banks of memory, to facilitate bank-specific addressing for memory array operations. In some embodiments, the electronic memory can facilitate status information for subsets of memory banks to facilitate informed array operations, increasing duty cycle of the memory device.

Abstract: Two-terminal memory can be formed into a memory array that contains many discrete memory cells in a physical and a logical arrangement. Where each memory cell is isolated from surrounding circuitry by a single transistor, the resulting array is referred to as a 1T1R memory array. In contrast, where a group of memory cells are isolated from surrounding circuitry by a single transistor, the result is a 1TnR memory array. Because memory cells of a group are not isolated among themselves in the 1TnR case, bit disturb effects are theoretically possible when operating on a single memory cell. Read operations are disclosed for two-terminal memory devices configured to mitigate bit disturb effects, despite a lack of isolation transistors among memory cells of an array. Disclosed operations can facilitate reduced bit disturb effects even for high density two-terminal memory cell arrays.

Abstract: Providing an electrode for a two-terminal memory device is described herein. By way of example, the electrode can comprise a contact surface that comprises at least one surface discontinuity. For instance, the electrode can have a gap, break, or other discontinuous portion of a surface that makes electrical contact with another component of the two-terminal memory device. In one example, the contact surface can comprise an annulus or an approximation of an annulus, having a discontinuity within a center of the annulus, for instance. In some embodiments, a disclosed electrode can be formed from a conductive layer deposited over a non-continuous surface formed by a via or trench in an insulator, or over a pillar device formed from or on the insulator.

Abstract: Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

Abstract: A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor.

Abstract: A configuration bit for a switching block routing array comprising a non-volatile memory cell is provided. By way of example, the configuration bit and switching block routing array can be utilized for a field programmable gate array, or other suitable circuit(s), integrated circuit(s), application specific integrated circuit(s), electronic device or the like. The configuration bit can comprise a switch that selectively connects or disconnects a node of the switching block routing array. A non-volatile memory cell connected to the switch can be utilized to activate or deactivate the switch. In one or more embodiments, the non-volatile memory cell can comprise a volatile resistance switching device connected in serial to a gate node of the switch, configured to trap charge at the gate node to activate the switch, or release the charge at the gate node to deactivate the switch.

Abstract: Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.

Abstract: Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.

Abstract: A two-terminal memory device can be formed according to a manufacturing process that utilizes two distinct chemical-mechanical planarization (CMP) processes for each of bottom electrode/terminal (BE) and the top electrode/terminal (TE). The CMP processes can reduce planar height variations for a top surface of the BE and a top surface of the TE. The CMP processes can reduce height differences between the top surface of the BE and adjacent dielectric surfaces and reduce height differences between the top surface of the TE and adjacent dielectric surfaces.

Abstract: A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, coupling a second electrode of the first resistive element, and a first electrode of the second resistive element to a first terminal of a first transistor element, coupling a second terminal of the first transistor element to a first terminal of a latch, coupling a second terminal of the latch to a gate of a second transistor element, and coupling a gate of the first transistor element to a latch program signal.

Abstract: A method for an FPGA includes programming a RRAM memory array with a first bit pattern, shifting the first bit pattern to a shift register array, employing the first bit pattern in operation of the FPGA, programming a RRAM memory array with a second bit pattern concurrent the employing the bit pattern in operation of the FPGA, shifting the second bit pattern to the shift register array, and employing the second bit pattern in operation of the FPGA.

Abstract: A memory system includes a memory device. The memory device includes a substrate. A memory array defines a plurality of pages, each page including a data area for storing data and a spare area for storing a program/erase (PE) count value, the PE count value indicating a number of PE cycles performed on the page. A PE count circuit is configured to perform a PE count read operation on a target page. A host determines whether to perform a data write operation on the target page or another PE count read operation on a new target page based on a result of the PE count read operation. PE cycles of a page are controlled by the PE count read operation. The memory array and the PE count circuit are formed in different layers of the substrate.

Abstract: Providing for a non-volatile buffer for a data storage device is disclosed herein. By way of example, the non-volatile buffer can save data that is to be written to a high-capacity data storage device. By utilizing non-volatile memory for the buffer, write caching operations can be streamlined, allowing a host to de-allocate memory more quickly as compared with volatile buffer memory, while reducing or avoiding hardware (e.g., capacitors) utilized to provide temporary power to volatile memory. In one example, the non-volatile buffer can comprise two-terminal, resistive switching memory having high read and write performance. Such a buffer can facilitate caching operations at speeds suitable for modern high-capacity storage devices.

Abstract: A method of forming a non-volatile memory device, includes forming a first electrode above a substrate, forming a dielectric layer overlying the first electrode, forming an opening structure in a portion of the dielectric layer to expose a surface of the first electrode having an aspect ratio, forming a resistive switching material overlying the dielectric layer and filling at least a portion of the opening structure using a deposition process, the resistive switching material having a surface region characterized by a planar region and an indent structure, the indent structure overlying the first electrode, maintaining a first thickness of resistive switching material between the planar region and the first electrode, maintaining a second thickness of resistive switching material between the indent structure and the first electrode, wherein the first thickness is larger than the second thickness, and forming a second electrode overlying the resistive switching material including the indent structure.

Abstract: A retainer node circuit is provided that can retain state information of a volatile circuit element (e.g., a flip-flop, latch, switch, register, etc.) of an electronic device for planned or unplanned power-down events. The retainer node circuit can include a resistive-switching memory cell that is nonvolatile, having very fast read and write performance. Coupled with power management circuitry, the retainer node circuit can be activated to receive and store a signal (e.g., bit) output by the volatile circuit element, and activated to output the stored signal. Various embodiments disclose non-volatile retention of state information for planned shut-down events as well as unplanned shut-down events. With read and write speeds in the tens of nanoseconds, sleep mode can be provided for volatile circuit elements between clock cycles of longer time-frame applications, enabling intermittent power-down events between active periods. This enables reduction in power without loss of activity for an electronic device.

Abstract: Providing for a memory apparatus comprising multiple banks of non-volatile memory and a high-speed data bus is described herein. By way of example, the memory apparatus can employ a standard or near-standard DRAM bus as an interface to high-performance two-terminal memory arrays. Interleaved operation can facilitate throughputs over 2gigabytes/second, in various embodiments, and larger throughputs in at least some embodiments, by interleaving multiple memory banks that are separately addressed via one or more mode registers, referred to as an index register(s). Further, the memory apparatus can have one or two terabytes of total storage, with capacity to increase storage volume. According to various embodiments, the memory apparatus can operate with a standard DRAM controller, or a memory controller configured with a DRAM communication protocol, modified in software or firmware to match configurations of the non-volatile memory employed for the multiple banks of memory.

Abstract: Providing for a memory apparatus configured for improved data management for a two-terminal memory array is described herein. By way of example, disclosed embodiments relate to page management and transfer of data between page-sized subsets of a page buffer, and respective pages within one or more memory banks of the two-terminal memory array. The memory apparatus can emulate a larger page size than a physical page buffer utilized by the memory apparatus, to provide compatibility with different page size defaults while lowering current consumption by the page buffer. This can facilitate large or small array operations, taking advantage of higher efficiencies of two-terminal memory devices. In addition, page buffer data management can facilitate interleaved data transfers among multiple banks of memory, facilitating large memory capacities for a disclosed memory apparatus.

Abstract: Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

Abstract: A method of forming a disturb-resistant non volatile memory device includes providing a substrate and forming a first dielectric thereon, forming a first strip of material separated from a second strip of material from a first wiring material, and forming a second dielectric thereon to fill a gap between the first and second strips of material. Openings are formed in the second dielectric exposing portions of the first wiring material. Filing the openings by p+ polysilicon contact material, and then an undoped amorphous silicon material, and then a metal material. A second wiring structure is formed thereon to contact the metal material in the openings. Resistive switching cells are formed from the first wiring structure, the second wiring structure, the contact material, the undoped amorphous silicon material, and the metal material.