Abstract: Two-terminal memory can be set to a first state (e.g., conductive state) in response to a program pulse, or set a second state (e.g., resistive state) in response to an erase pulse. These pulses generally provide a voltage difference between the two terminals of the memory cell. Certain electrical characteristics associated with the pulses can be manipulated in order to enhance the efficacy of the pulse. For example, the pulse can be enhanced or improved to reduce power-consumption associated with the pulse, reduce a number of pulses used to successfully set the state of the memory cell, reduce wear or damage to the memory cell, or to improve Ion or Ioff distribution associated with changing the state of the memory cell.

Abstract: A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first electrode structure is formed overlying the first dielectric material and a p+ polycrystalline silicon germanium material is formed overlying the first electrode structure. A p+ polycrystalline silicon material is formed overlying the first electrode structure using the polycrystalline silicon germanium material as a seed layer at a deposition temperature ranging from about 430 Degree Celsius to about 475 Degree Celsius without further anneal. The method forms a resistive switching material overlying the polycrystalline silicon material, and a second electrode structure including an active metal material overlying the resistive switching material.

Abstract: Mechanisms or techniques for improving operations such as program or erase operations that are intended to set a state of one or more multi-level memory cells (MLC) to a selected or designated state. For example, a first voltage pulse can be applied to an MLC that is intended to set the MLC to a desired state. Thereafter, a sensing pulse can be applied to the MLC, and one or more suitable electrical characteristic (EC) such as resistance can be measured and reported. This measured EC can then be compared to thresholds that define the range of acceptable values for the EC in order for the MLC to be deemed to be in the selected state. If the measured EC is not within the suitable range threshold, then one or more additional voltage pulses can be applied in order to properly set the MLC to the designated state and these additional voltages pulses can have different characteristics than the first voltage pulse.

Abstract: Providing a high-density two-terminal memory architecture(s) having performance benefits of two-terminal memory and relatively low fabrication cost, is described herein. By way of example, the two-terminal memory architecture(s) can be constructed on a substrate, in various embodiments, and comprise two-terminal memory cells formed within conductive layer recess structures of the memory architecture. In one embodiment, a conductive layer recess can be created as a horizontal etch in conjunction with a vertical via etch. In another embodiment, the conductive layer recess can be patterned for respective conductive layers of the two-terminal memory architecture.

Abstract: Disclosed is a solid state memory having a non-linear current-voltage (I-V) response. By way of example, the solid state memory can be used as a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the nonvolatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

Abstract: A switching device includes a first dielectric material formed overlying a substrate. A bottom wiring material and a switching material are sequentially formed overlying the first dielectric material. The bottom wiring material and the switching material are patterned and etched to form a first structure having a top surface region and a side region. The first structure includes a bottom wiring structure and a switching element having the top surface region including an exposed region. A second dielectric material is formed overlying the first structure. A first opening region is formed in a portion of the second dielectric layer to expose a portion of the top surface region. A dielectric side wall structure is formed overlying a side region of the first opening region. A top wiring material including a conductive material is formed overlying the top surface region to be directly contact with the switching element.

Abstract: Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.

Abstract: Operating characteristics associated with non-volatile two-terminal memory can be modified post-fabrication, e.g., by a controller that controls the non-volatile two-terminal memory. As a result, two-terminal memory arrays included in memory devices (e.g., memory cards, solid-state drives, etc.) can be flexibly modified to provide numerous advantages over other types of non-volatile memory.

Abstract: Providing for a two-terminal memory cell having intrinsic current limiting characteristic is described herein. By way of example, the two-terminal memory cell can comprise a particle donor layer having a moderate resistivity, comprised of unstable or partially unstable metal compounds. The metal compounds can be selected to release metal atoms in response to an external stimulus (e.g., an electric field, a voltage, a current, heat, etc.) into an electrically-resistive switching medium, which is at least in part permeable to drift or diffusion of the metal atoms. The metal atoms form a thin filament through the switching medium, switching the memory cell to a conductive state. The moderate resistivity of the particle donor layer in conjunction with the thin filament can result in an intrinsic resistance to current through the memory cell at voltages above a restriction voltage, protecting the memory cell from excessive current.

Abstract: A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.

Abstract: A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, applying a first programming voltage to a shared node of a second electrode of the first resistive element, a first electrode of the second resistive element, and to a gate of a transistor element, and changing a resistance state of the first resistive element to a low resistance state while maintaining a resistance state of the second resistive element, when a voltage difference between the first programming voltage at the second terminal and the first input voltage at the first terminal exceeds a programming voltage associated with the first resistive element.

Abstract: Operating characteristics associated with NAND flash memory can be modified and/or emulated to support corresponding operating characteristics for two-terminal memory. As a result, NAND flash memory modules included in conventional NAND flash memory devices (e.g., memory cards, solid-state drives, etc.) can be replaced with two-terminal memory without substantial changes to manufacturing infrastructure associated with the manufacture of these NAND flash memory devices.

Abstract: Providing for a monolithic memory device comprising a combination of a one-transistor, one-resistor (1T1R) memory array, and a one-transistor, multiple-resistor (1TnR, where n is a suitable integer greater than 1) memory array is described herein. By way of example, the monolithic memory device can be a stand-alone device, configured to perform functions in response to predetermined conditions and generate an output(s), or can be a removable device that can be connected to and operable with another device. In various embodiments, the 1TnR array having high memory density can serve as storage class memory (SCM) for the monolithic memory device, and the 1T1R array having high performance and efficacy can serve as code memory. In addition to the foregoing, the 1T1R array and the 1TnR array can be fabricated from at least one common layer or a common processing step, to simplify and lower cost of fabricating disclosed memory devices.

Abstract: A high density non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a resistive two-terminal selector that can be in a low resistive state or a high resistive state depending on the voltage being applied. A deep trench MOS (“metal-oxide-semiconductor”) transistor having a floating gate with small area relative to conventional devices can be provided, in addition to a capacitor or transistor acting as a capacitor. A first terminal of the capacitor can be connected to a voltage source, and the second terminal of the capacitor can be connected to the selector device. The small area floating gate of the deep trench transistor can be connected to the other side of the selector device, and a second transistor can be connected in series with the deep trench transistor.

Abstract: Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.

Abstract: A circuit operable as a non-volatile memory cell, formed in part from a volatile selection device, is provided. The circuit can be fabricated utilizing Integrated Circuit (IC)-Foundry compatible processes to simplify manufacturing, reduce cost and improve yield. For instance, the circuit can comprise a set of transistors fabricated at least in part with front-end-of-line IC processes, and can comprise the volatile selection device and a set of interconnects fabricated at least in part with back-end-of-line IC processes. In further embodiments, the volatile selection device can be a two-terminal, volatile resistive-switching device connected at one end to a gate of an n-well transistor, and connected at a second end to a gate of a p-well transistor.

Abstract: A method for forming a resistive memory device includes providing a substrate comprising a first metal material, forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the lower region is adjacent to the first metal material, forming an amorphous layer from the upper region of the conductive silicon-bearing layer, and disposing an active metal material above the amorphous layer.

Abstract: A non-volatile programmable circuit configurable to perform logic functions, is provided. The programmable circuit can employ two-terminal non-volatile memory devices to store information, thereby mitigating or avoiding disturbance of programmed data in the absence of external power. Two-terminal resistive switching memory devices having high current on/off ratios and fast switching times can also be employed for high performance, and facilitating a high density array. For look-up table applications, input/output response times can be several nanoseconds or less, facilitating much faster response times than a memory array access for retrieving stored data.

Abstract: A detection circuit that can detect a two-terminal memory cell changing state. For example, in response to electrical stimuli, a memory cell will change state (e.g., to a highest resistance state), but existing techniques do not detect this state change until after the stimuli is completed and a subsequent sensing operation (e.g., read pulse) is performed. The detection circuit can detect the state change during application of the electrical stimuli that causes the state change.

Abstract: A method of forming a memory device includes providing a substrate having a surface region, defining a cell region and first and second peripheral regions, sequentially forming a first dielectric material, a first wiring structure for a first array of devices, and a second dielectric material over the surface region, forming an opening region in the first peripheral region, the opening region extending in a portion of at least the first and second dielectric materials to expose portions of the first wiring structure and the substrate, forming a second wiring material that is overlying the second dielectric material and fills the opening region to form a vertical interconnect structure in the first peripheral region, and forming a second wiring structure from the second wiring material for a second array of devices, the first and second wiring structures being separated from each other and electrically connected by the vertical interconnect structure.