Abstract: A three-terminal bidirectional GaN FET with a single gate. The device is formed by integrating a single-gate bidirectional GaN FET in parallel with a bidirectional device formed of two back-to-back GaN FETs with a source that is connected to the field plate of the device and does not have a pin-out. Diodes or gate-shorted-to-source FETs are connected between the source without pin-out and the D/S and S/D power terminals of the device. In another embodiment, a single-gate bidirectional GaN FET is provided with diodes or gate-shorted-to-source FETs connected between the substrate and the power terminals of the device.

Abstract: A driver circuit for a solid-state relay which includes a split power supply. The positive supply of the split power supply provides a voltage for application to the gate of a power FET for supplying power to a load. The negative supply of the split power supply provides a negative voltage for turning off a control transistor. The control transistor prevents the power FET from conducting power to the load when the driver circuit is turned off. The circuit is particularly adapted for driving a power GaN FET solid state relay. The circuit is provided in a cascaded embodiment to increase the blocking voltage of the solid-state relay.

Abstract: A gate driver circuit which integrates a synchronous bootstrap circuit in an isolation well of an integrated circuit, such that the synchronous bootstrap capacitor connected to the synchronous bootstrap circuit (and to the corresponding switch node of a power converter) can float with the corresponding switch node. Due to this feature, the voltage on one synchronous bootstrapping capacitor can be used to charge the synchronous bootstrapping capacitor of another (higher level) synchronous bootstrap circuit in a separate isolation well connected to a different switch node. As a result, the supply voltages for the synchronous bootstrap circuits in different isolation wells can all be supplied from a single ground referenced supply Vdd.

Abstract: An integrated current sensing amplifier with offset cancellation implemented in GaN technology. The current sensing amplifier senses the current flowing through a low side power FET or a high side power FET of a half bridge circuit. The current sensing amplifier uses the off time of the power FET for storing the amplifier input offset voltage. The stored amplifier input offset voltage is then used to cancel the amplifier input offset voltage during the on time of the power FET, which is the interval that requires current sensing.

Abstract: A single-ended or differential level-shifting interface for GaN ICs that allows GaN ICs to be controlled with standard low-voltage CMOS level inputs. The logic level shift circuit is based on a resistive network is therefore insensitive to process and temperature variations, making it particularly well suited for implementation in a GaN IC. The resistive network for a single-ended input signal includes a first branch with a voltage divider connected to the input signal. The voltage divider of the first branch provides a level shifted and scaled input signal to the first input of a comparator at the optimal bias point of the comparator. The resistive network also includes a second voltage divider branch with hysteresis for providing a trip voltage to the second input to the comparator, also at the optimal bias point of the comparator. The comparator outputs complementary bipolar level shifted signals corresponding to the input signal.

Abstract: A multi-channel current pulse generator for driving a plurality of loads with unique positive terminals and a shared negative terminal. The pulse generator comprises a pulse control transistor and, for each load, a load capacitor and a charging control transistor. The pulse control transistor allows or blocks current pulses through the loads and has a drain terminal connected to the shared negative terminal, a source terminal connected to ground, and a gate terminal for receiving a load driver control signal. The load capacitors are discharged by current pulses through the corresponding loads. The charging control transistors allow or block charging currents for the corresponding load capacitors. The pulse control transistor is preferably an enhancement mode GaN FET and is chosen to withstand current pulses through a maximum number of loads to be driven simultaneously.

Abstract: A multi-level converter includes a flying capacitor and a resistive voltage divider. The multi-level converter is configured to convert an input voltage into an output voltage. The resistive voltage divider is configured to charge a flying capacitor in the multi-level converter during an initial charging mode of operation. In some implementations, the multi-level converter includes a plurality of flying capacitors and a plurality of resistive voltage dividers including a resistive voltage divider for each flying capacitor in the plurality of flying capacitors.

Abstract: A cross-coupled differential activated latch circuit with circuitry comprising a plurality of n-FETs and inverters that can be implemented completely in GaN. The circuitry prevents the digital latched values on the outputs of the latch from changing unless the digital input values on the inputs are different, thus preventing common-mode voltage on the inputs from corrupting the stored latch values.

Abstract: A gallium nitride (GaN) transistor which includes multiple insulator semiconductor interface regions. Two or more first insulator segments and two or more second insulator segments are positioned between the gate and drain contacts and interleaved together. At least one first insulator segment is nearer to the gate contact than the second insulator segments. At least one second insulator segment is nearer to the drain contact than the first insulator segments. The first and second insulators are chosen such that a net electron donor density above the channel under the first insulator segments is lower than a net electron density above the channel under the second insulator segments. The first insulator segments reduce gate leakage and electric fields near the gate that cause high gate-drain charge. The second insulator segments reduce electric fields near the drain contact and provide a high density of charge in the channel for reduced on-resistance.

Abstract: A lateral power semiconductor device with a metal interconnect layout for low on-resistance. The metal interconnect layout includes first, second, and third metal layers, each of which include source bars and drain bars. Source bars in the first, second, and third metal layers are electrically connected. Drain bars in the first, second, and third metal layers are electrically connected. In one embodiment, the first and second metal layers are parallel, and the third metal layer is perpendicular to the first and second metal layers. In another embodiment, the first and third metal layer are parallel, and the second metal layer is perpendicular to the first and third metal layers. A nonconductive layer ensures solder bumps electrically connect to only source bars or only drain bars. As a result, a plurality of available pathways exists and enables current to take any of the plurality of available pathways.

Abstract: An integrated circuit that includes a plurality of GaN transistor sets. A first set of the plurality of GaN transistor sets includes transistors with a first drain-to-source distance, and wherein a second of the plurality of GaN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance.

Abstract: An enhancement mode GaN FET based gate driver circuit including an active pre-driver to drive a high-slew rate, high current output stage GaN FET. Due to the active driver current from the pre-driver, the output stage pull-up FET can turn on faster as compared to a pre-driver that utilizes a passive pull-up load. The active pre-driver must provide a voltage to drive the gate of the output stage pull-up FET which is higher than the normal supply voltage to enable the maximum output level of the driver FET to approach the normal supply voltage. A feedback circuit is included in the active pre-driver to avoid the need for two supply voltages.

Abstract: A highly efficient, multi-layered, single component sided circuit board layout design providing reduced parasitic inductance for power switched circuits. Mounted on the top board are one or more transistor switches, one or more loads, and one or more capacitors. The switches and capacitors form a loop with very low parasitic inductance. The loads may be a part of the loop, i.e. in series with the switches and capacitors, or may be connected to two or more nodes of the loop to form additional loops with common vertices. Parallel wide conductors carry the switch load current resulting in a low inductance path for the power loop. The power loop and gate loop current travel in opposite directions and are well separated, minimizing common source inductance (CSI) and maximizing switching speed.

Abstract: A common gate amplifier circuit configured to provide decreased voltage transients in the input voltage due to reverse gain. A second FET transistor is connected in series with a first FET of the common gate amplifier to function as an additional capacitive voltage divider between the amplifier output and the amplifier input without influencing the input or output currents. The first FET transistor, coupled to the amplifier input, may be a low voltage FET and smaller than the second FET transistor, which is coupled to the amplifier output. Both FET transistors are preferably enhancement mode GaN FET transistors and may be integrated into a single semiconductor chip with a single internal bias voltage divider.

Abstract: A current measurement circuit for determining a start time tSTART, an end time tEND, and/or a peak time tMAX for a current pulse passing through a current conductor. The current measurement circuit includes a pickup coil and a threshold crossing detector. The pickup coil generates a voltage VSENSE? proportional to a magnetic field around the conductor, which is proportional to a change in current over time. The threshold crossing detector compares VSENSE? and a threshold voltage and generates an output signal indicative of a transition time and whether a slope of VSENSE? is positive or negative. The current measurement circuit can also include an integrator and a sample and hold circuit. The integrator integrates VSENSE? over time and generates an integrated signal VSENSE. The sample and hold circuit compares VSENSE to tMAX and generates a second output signal which can be used to measure the pulse current.

Abstract: A large area wireless power system having a synchronization transmitter and a plurality of synchronization receivers for receiving a plurality of differential signals from the synchronization transmitter and outputting a plurality of second single-ended signals. The synchronization transmitter generates a first single-ended signal and converts the first single-ended signal into the plurality of differential signals to be transmitted to the synchronization receivers over a plurality of differential line pairs that also provide power to the synchronization receivers. The large area wireless power system also includes a plurality of high power amplifiers for receiving the plurality of second single-ended signals from the respective synchronization receivers and generating power, and a plurality of wireless power coils for receiving the power generated by the plurality of high power amplifiers and wirelessly providing power.

Abstract: A scalable highly resonant wireless power coil structure that is suitable for use across a large surface area. The structure includes a plurality of single turn loops with adjacent loops that are decoupled from each other, yet form part of a single member.

Abstract: A laser-diode driver for Lidar applications with an output stage comprised of two enhancement mode GaN FETs. The output stage includes a driver GaN FET in a traditional common-source configuration, with the drain connected to the cathode of a laser diode and the source connected to ground. The gate of the driver GaN FET is driven by the source of the second, substantially smaller GaN FET in a source-follower configuration, rather than being driven directly by a pre-driver. The source-follower GaN FET has its drain connected to the drain of the common-source driver GaN FET, similar to a Darlington connection used in bipolar devices. The input drive signal from the pre-driver is applied at the gate of the source-follower GaN FET. The current required to turn on the driver GaN FET is thereby drawn from a main power supply through the laser diode, rather than from the power supply for the pre-driver, improving overall current efficiency.

Abstract: A wireless power receiver circuit includes an active rectifier circuit with a plurality of power transistors, wherein the active rectifier circuit is configured to rectify an induced AC receiver current. The wireless power receiver circuit includes also includes a gate drive controller circuit configured to sense the induced AC receiver current and to provide gate drive signals for the plurality of power transistors synchronized with the induced AC receiver current. The gate drive controller circuit includes a current sense circuit configured to provide two voltage signals having a difference proportional to the induced AC receiver current.

Abstract: A current pulse generator circuit configured to be monolithically integrated into a single semiconductor die and provide high pulsing frequencies. A first GaN FET transistor controls the charging of a capacitor in a boost converter. A second GaN FET transistor controls the discharging of the capacitor through a load, such as a laser diode, connected to the boost converter. Both GaN FET transistors are preferably enhancement mode GaN FETs and may be integrated into the single semiconductor die, together with gate drivers. The diode in a conventional boost converter circuit can also be implemented in the present invention as a GaN FET transistor, and also integrated into the single semiconductor die.