Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self- aligned ledges that extend toward the source contact and drain contact, respectively.

Abstract: An electrical circuit arranged in a half bridge topology. The electrical circuit includes a high side transistor; a low side transistor; a gate driver and level shifter electrically coupled to a gate of the high side transistor; a gate driver electrically coupled to a gate of the low side transistor; a capacitor electrically coupled in parallel with the gate driver and level shifter; a voltage source electrically coupled to an input of the gate driver and level shifter and an input of the gate driver; and, a bootstrap transistor electrically coupled between the voltage source and the capacitor. A GaN field-effect transistor is synchronously switched with a low side device of the half bridge circuit.

Abstract: A power factor correction (PFC) boost circuit. The PFC boost circuit can include a first switching device, a second switching device, a first gate driver coupled to the first switching device, a second gate driver coupled to the second switching device, and a PFC controller configured to control the first and second gate drivers. The PFC controller will utilize a new technique, referred to herein as “predictive diode emulation” to control the switching devices in a desired manner and to overcome inefficiencies and other problems that might arise using traditional diode emulation. The PFC controller is configured to operate in synchronous and non-synchronous modes.

Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.

Abstract: A circuit and technique are provided to control bias setting to an FET based common source RF amplifier that can operate with large signals present. The circuit and technique described herein use a second FET in an identical circuit having the gate circuits connected in parallel and being sourced by the same drain voltage that serves as a reference to a first circuit bias setting. The drain current in a first FET will include both the bias and RF amplification current, whereas the second FET only carries the bias current. Because the devices and circuits are matched, the gate voltage variations will appear in both FETs thereby providing regulation of the drain current.

Abstract: A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor.

Abstract: Parallel transistor circuits with reduced effects from common source induction. The parallel transistors include physical gate connections that are located electrically close to one another. The parallel circuits are arranged such that the voltage at the common gate connection resulting from transient currents across common source inductance is substantially balanced. The circuits include switching circuits, converters, and RF amplifiers.

Abstract: A method for forming an enhancement mode GaN HFET device with an isolation area that is self-aligned to a contact opening or metal mask window. Advantageously, the method does not require a dedicated isolation mask and the associated process steps, thus reducing manufacturing costs. The method includes providing an EPI structure including a substrate, a buffer layer a GaN layer and a barrier layer. A dielectric layer is formed over the barrier layer and openings are formed in the dielectric layer for device contact openings and an isolation contact opening. A metal layer is then formed over the dielectric layer and a photoresist film is deposited above each of the device contact openings. The metal layer is then etched to form a metal mask window above the isolation contact opening and the barrier and GaN layer are etched at the portion that is exposed by the isolation contact opening in the dielectric layer.

Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.

Abstract: An integrated semiconductor device which includes a substrate layer, a buffer layer formed on the substrate layer, a gallium nitride layer formed on the buffer layer, and a barrier layer formed on the gallium nitride layer. Ohmic contacts for a plurality of transistor devices are formed on the barrier layer. Specifically, a plurality of first ohmic contacts for the first transistor device are formed on a first portion of the surface of the barrier layer, and a plurality of second ohmic contacts for the second transistor device are formed on a second portion of the surface of the barrier layer. In addition, one or more gate structures formed on a third portion of the surface of the barrier between the first and second transistor devices. Preferably, the one or more gate structures and the spaces between the gate structures and the source contacts of the transistor devices collectively form an isolation region that electrically isolates the first transistor device from the second transistor device.

Abstract: A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer.

Abstract: An enhancement mode GaN transistor having a gate pGaN structure having a thickness which avoids dielectric failure. In one embodiment, this thickness is in the range of 400 ? to 900 ?. In a preferred embodiment, the thickness is 600 ?.

Abstract: A power factor correction (PFC) boost circuit. The PFC boost circuit can include a first switching device, a second switching device, a first gate driver coupled to the first switching device, a second gate driver coupled to the second switching device, and a PFC controller configured to control the first and second gate drivers. The PFC controller will utilize a new technique, referred to herein as “predictive diode emulation” to control the switching devices in a desired manner and to overcome inefficiencies and other problems that might arise using traditional diode emulation. The PFC controller is configured to operate in synchronous and non-synchronous modes.

Abstract: An enhancement-mode GaN transistor. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.

Abstract: A self-aligned transistor gate structure that includes an ion-implanted portion of gate material surrounded by non-implanted gate material on each side. The gate structure may be formed, for example, by applying a layer of GaN material over an AlGaN barrier layer and implanting a portion of the GaN layer to create the gate structure that is laterally surrounded by the GaN layer.

Abstract: Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability.

Abstract: A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device.

Abstract: A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer.

Abstract: An enhancement-mode GaN transistor. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.