Abstract: An enhancement-mode GaN transistor, the transistor having a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate containing acceptor type dopant elements, and a diffusion barrier comprised of a III Nitride material between the gate and the buffer layer.
Type:
Grant
Filed:
April 7, 2010
Date of Patent:
May 7, 2013
Assignee:
Efficient Power Conversion Corporation
Inventors:
Alexander Lidow, Robert Beach, Guang Y. Zhao, Jianjun Cao
Abstract: An enhancement mode gallium nitride (GaN) transistor with a Mg doped layer and a Mg growth interruption (diffusion barrier) layer to trap excess or residual Mg dopant. The Mg growth interruption (diffusion barrier) layer is formed by growing GaN, stopping the supply of gallium while maintaining a supply of ammonia or other nitrogen containing source to form a layer of magnesium nitride (MgN), and then resuming the flow of gallium to form a GaN layer to seal in the layer of MgN.
Abstract: An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.
Type:
Grant
Filed:
April 8, 2010
Date of Patent:
March 26, 2013
Assignee:
Efficient Power Conversion Corporation
Inventors:
Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao, Guang Yuan Zhao
Abstract: A MISFET, such as a GaN transistor, with low gate leakage. In one embodiment, the gate leakage is reduced with a compensated GaN layer below the gate contact and above the barrier layer. In another embodiment, the gate leakage is reduced by employing a semi-insulating layer below the gate contact and above the barrier layer.
Type:
Grant
Filed:
April 8, 2010
Date of Patent:
January 8, 2013
Assignee:
Efficient Power Conversion Corporation
Inventors:
Alexander Lidow, Robert Beach, Jianjun Cao, Alana Nakata, Guang Yuan Zhao