Abstract: The present application describes an apparatus and method for reducing distortion in a class-D amplifier. The power output section of the amplifier is driven by an adjusted PWM signal, rather than by a PWM signal created directly from the input analog signal. A reference output, designed to closely track the input analog signal, is compared to the amplifier output. The resulting difference is an error signal which is inverted and summed with a second analog signal corresponding to the directly created PWM signal and changes the timing of the voltage transitions of the second analog signal. The changed voltage transitions are used to create the adjusted PWM signal. The inversion of the error signal causes negative feedback which results in the adjustment of the PWM signal being in a direction which reduces the error signal and thus the distortion of the amplifier.

Abstract: A finite impulse response (FIR) filter having a differential output and capable of having negative coefficients, and a method of designing the filter, is disclosed. In contrast to the prior art, in which two output signals requires the use of two identical sets of impedance devices corresponding to the Fourier coefficients that create the desired response of the filter, the described method and system uses only a single set of impedance devices, and thus approximately one-half of the number of impedance devices used in the prior art. This is accomplished by appropriately selecting which resistors contribute to which output, so that a differential output may be obtained that is substantially the same as if impedance devices corresponding to all of the coefficients were used for each signal.

Abstract: A method and system for generating and matching complex series and/or parallel combinations of nominally identical initial elements to achieve compound values having constant ratios to the initial elements and to each other is disclosed. The ratios between compound values can be held constant to almost any desired degree of accuracy, with potential errors greatly reduced from those typical in the construction of individual elements of different values. Since the initial elements are nominally identical, the ratios between values depend primarily upon the connections of the initial elements, rather than their geometry, and thus remain virtually constant regardless of variations in the manufacturing process.

Abstract: A method and system is disclosed for designing a radio for down-converting RF signals to IF signals by sampling the signals in a round-robin sampling circuit and multiplying the samples by coefficients that are changed at a fixed rate equal to the rate of operation of each of the sampling circuits. The circuit is able to down-convert multiple channels simultaneously to adjacent positions in the IF band, while rejecting unwanted image signals. The method and system avoids the difficulty and cost of directly digitizing the RF signal, allowing each component to operate at a greatly reduced speed. The coefficients are selected to provide the desired transfer function while keeping the output signal centered at a desired frequency.

Abstract: The present application describes an apparatus and method for improving the performance of ?? modulators functioning as ADCs. In one embodiment, the ?? modulator comprises a plurality of quantizers operating in a round-robin fashion, rather than the single quantizer of the prior art. The use of multiple quantizers allows the ?? modulator to appear to be functioning at a significantly higher rate than a single quantizer allows. In another embodiment, a second-order ?? modulator contains a plurality of control loops, rather than the single control loop of the prior art. The use of multiple control loops allows the ?? modulator to have multiple points of maximum signal-to-noise ratio rather than a single such point as in prior art ?? modulators.

Abstract: This application relates to decoding signals that carry clock and data information. In particular, it relates to construction a time-varying histogram of inter-arrival times between pulse edges and using the histogram to identify whether a pulse edge encodes a single length interval, a double length interval or some longer length interval. Further details and embodiments of the technology disclosed are provided in the drawings, detailed description and claims.

Abstract: A virtual Weaver architecture filter is implemented using a sampling mixer that successively processes samples of the input signal in round-robin fashion and provides a sum of the samples as multiplied by coefficients emulating quadrature sinusoidal waveforms. A virtual rather than actual local oscillator is reliably implemented without mismatch. Filtering between the Weaver mixers is eliminated in favour of filtering at the sampling input and effective time division multiplexing is achieved by selecting between resistor combinations that implement different scaling coefficients, resulting in an efficient analog implementation of a virtual Weaver architecture.

Abstract: A method and system for designing and implementing a finite impulse response (FIR) filter to create a plurality of output signals, each output signal having the same frequency but at a different phase shift from the other output(s), is described. Values are determined for the resistors, or other elements having impedance values, in a FIR filter having a plurality of outputs, such that each output has the same frequency response but a different phase than the other output(s). This is accomplished by the inclusion of a phase factor in the time domain calculation of the resistor values that does not change the response in the frequency domain. The phase shift is constant and independent of the frequency of the output signal.

Abstract: A method and system for generating and matching complex series and/or parallel combinations of nominally identical initial elements to achieve compound values having constant ratios to the initial elements and to each other is disclosed. The ratios between compound values can be held constant to almost any desired degree of accuracy, with potential errors greatly reduced from those typical in the construction of individual elements of different values. Since the initial elements are nominally identical, the ratios between values depend primarily upon the connections of the initial elements, rather than their geometry, and thus remain virtually constant regardless of variations in the manufacturing process.

Abstract: A finite impulse response (FIR) filter having a differential output and capable of having negative coefficients, and a method of designing the filter, is disclosed. In contrast to the prior art, in which two output signals requires the use of two identical sets of impedance devices corresponding to the Fourier coefficients that create the desired response of the filter, the described method and system uses only a single set of impedance devices, and thus approximately one-half of the number of impedance devices used in the prior art. This is accomplished by appropriately selecting which resistors contribute to which output, so that a differential output may be obtained that is substantially the same as if impedance devices corresponding to all of the coefficients were used for each signal.

Abstract: There is provided a CMOS imager system for providing a viewable image having increased dynamic range including an image sensor including a number of sets of pixels. Each set of pixels is configured to receive one of a number of exposures and to generate image data corresponding to the received exposure in the interleaved mode. The image sensor is configured to operate in either an interleaved mode or a non-interleaved mode and to output the image data generated by each set of pixels as a frame of interleaved image data in the interleaved mode. The imager system further includes an interleaved image pipeline in communication with the image sensor, where the interleaved image pipeline is configured to receive the interleaved image data from the image sensor, combine the image data generated by each set of pixels corresponding to one of the exposures to form the viewable image.

Abstract: An opportunity is apparent to develop alternative circuitry. Simplified circuitry without artifacts tied to the clock that drives a digital frequency generator (DFG) is useful in a variety of tunable electronic devices. The present invention relates to digital frequency generation. In particular, it relates to a method and apparatus for the digital generation of a pulse stream having a desired frequency relative to a reference clock signal and the ratio of two integers. The method applies generally to integers whose ratio is not an integer. The DFG as a device can be integrated onto a simple chip, without need for an off-chip filter.

Abstract: An electronic filter operates as a correlator that provides a discrete approximation of an analog signal. The analog to digital conversion is integrated directly approximation calculation. An array of sample and hold circuits or single bit comparators provide outputs to a series of multipliers, the other input of which is a coefficient value of a Fourier series approximation of the desired frequency response. Each of the sample and hold circuits samples sequentially in time and holds its sample until the next cycle. Thus the sample point rotates in time through the array and each new sample is multiplied by a different coefficient. The output of the multipliers is summed for evaluation.

Abstract: A digital frequency generator is described.

Abstract: Multi-phase integrators in control systems are described.

Abstract: The technology relates to analog processing of a sum of products.

Abstract: An opportunity is apparent to develop alternative circuitry. Simplified circuitry without artifacts tied to the clock that drives a digital frequency generator (DFG) is useful in a variety of tunable electronic devices. The present invention relates to digital frequency generation. In particular, it relates to a method and apparatus for the digital generation of a pulse stream having a desired frequency relative to a reference clock signal and the ratio of two integers. The method applies generally to integers whose ratio is not an integer. The DFG as a device can be integrated onto a simple chip, without need for an off-chip filter.

Abstract: A multiphase clock generates pulses at a rate much higher than the clock frequency.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: A system is provided for use in an audio signal processor to reduce the order of the loop to remove sound artifacts from an audio signal that includes an input for receiving an audio input signal a control loop of order greater than one configured to process the audio input signal and to output a Pulse Width Modulated audio output signal, a circuit for performing a gradual reduction of the order of the control loop such that prior to entering a shut down state the order is reduced to a single order and a circuit to disconnect a Driver Circuit from the Pulse Width modulated signal operated by a timing device designed to switch at the moment of zero average output value.