Patents Assigned to ESS Technology, Inc.
  • Method and apparatus for controlling charge transfer in CMOS sensors with an implant by the transfer gate
    Patent number: 7755116
    Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: July 13, 2010
    Assignee: ESS Technology, Inc.
    Inventors: Zeynep Toros, Richard Mann, Selim Bencuya
  • Wide dynamic range image sensor
    Patent number: 7745774
    Abstract: An exemplary image sensor comprises a photodetector proximate to a pixel site, and a light meter proximate to the pixel site configured to approximate an initial charge acquired by the photodetector at the end of a first integration period of a frame exposure period. A reset circuit resets the photodetector if the approximated initial charge acquired by the photodetector exceeds a threshold. A readout circuit detects a final charge acquired by the photodetector at the end of a second integration period of the frame exposure period. If the photodetector was reset, the readout circuit adjusts the final exposure to account for exposure prior to the photodetector having been reset.
    Type: Grant
    Filed: June 7, 2008
    Date of Patent: June 29, 2010
    Assignee: ESS Technology, Inc.
    Inventor: Richard A. Mann
  • Method and apparatus for controlling charge transfer in CMOS sensors with an implant by the transfer gate
    Publication number: 20100118173
    Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable description' s of the circuit.
    Type: Application
    Filed: December 4, 2009
    Publication date: May 13, 2010
    Applicant: ESS Technology, Inc.
    Inventors: Zeynep Toros, Richard Mann, Selim Bencuya
  • Spread spectrum clock generator having an adjustable delay line
    Patent number: 7680173
    Abstract: A system and method are provided for performing a spread spectrum clock generation, where the system includes self-adjusting delay line configured to spread the spectrum of a fixed circuit using a fixed clock frequency and a delay circuit configured to generate an adjustment signal to the delay line by adding or subtracting an addition delay per cycle, therefore causing a shift in the output clock frequency, wherein the amount of shift is proportional to the rate of addition or subtraction of delay.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: March 16, 2010
    Assignee: ESS Technology, Inc.
    Inventors: Andrew Martin Mallinson, Simon Damphousse
  • Method and apparatus for proximate CMOS pixels
    Patent number: 7635880
    Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: December 22, 2009
    Assignee: ESS Technology, Inc.
    Inventors: Zeynep Toros, Richard Mann, Selim Bencuya
  • Low noise digital to pulse width modulated converter with audio applications
    Patent number: 7570693
    Abstract: The present invention relates to digital-to-analog conversion. In particular, it has application to conversion of pulse code modulated signals, such as used in CDs and DVDs, to a pulse width modulated or analog signal.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: August 4, 2009
    Assignee: ESS Technology, Inc.
    Inventors: A. Martin Mallinson, Dustin D. Forman, Simon Damphousse
  • System and method for 3D sound processing
    Patent number: 7551741
    Abstract: A system for 3D sound processing. The system includes a first processing section including a first left lattice filter and a first right lattice filter, respectively electrically connected to a second left lattice filter and a second right lattice filter, and including two negative couplers, each electrically connected to the first left and right lattice filters and also electrically connected to the second left and right lattice filters, and a second processing section including a left filter and a right filter, respectively electrically connected to the second left lattice filter and the second right lattice filter.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: June 23, 2009
    Assignee: ESS Technology, Inc.
    Inventor: Qinglin Zhu
  • Method and apparatus for controlling charge transfer in CMOS sensors with a graded transfer-gate work-function
    Patent number: 7495274
    Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: February 24, 2009
    Assignee: ESS Technology, Inc.
    Inventors: Zeynep Toros, Richard Mann, Selim Bencuya
  • Bi-quad digital filter configured with a bit binary rate multiplier
    Patent number: 7457836
    Abstract: The invention is directed to a bi-quad filter circuit configured with sigma-delta devices that operate as binary rate multipliers (BRMs). Unlike conventional bi-quad filter circuits, the invention provides a bi-quad filter configured with a single-bit BRM. In another embodiment, the invention further provides a bi-quad filter configured with multiple-bit BRMs.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: November 25, 2008
    Assignee: ESS Technology, Inc.
    Inventor: Andrew Martin Mallinson
  • DIGITAL FORCED OSCILLATION BY DIRECT DIGITAL SYNTHESIS
    Publication number: 20080285698
    Abstract: An opportunity is apparent to develop alternative circuitry. Simplified circuitry without artifacts tied to the clock that drives a digital frequency generator (DFG) is useful in a variety of tunable electronic devices. The present invention relates to digital frequency generation. In particular, it relates to a method and apparatus for the digital generation of a pulse stream having a desired frequency relative to a reference clock signal and the ratio of two integers. The method applies generally to integers whose ratio is not an integer. The DFG as a device can be integrated onto a simple chip, without need for an off-chip filter.
    Type: Application
    Filed: May 18, 2007
    Publication date: November 20, 2008
    Applicant: ESS Technology, Inc.
    Inventor: Martin Mallinson
  • Asynchronous sample rate converter
    Patent number: 7436333
    Abstract: Various embodiments perform sample rate conversion of a sample series at an input rate to an output rate. A version of the sample series is corrected with timing error information generated by a digital loop. The digital loop is locked to a first rate and clocked at a second rate.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: October 14, 2008
    Assignee: ESS Technology, Inc.
    Inventors: Dustin D. Forman, Andrew Martin Mallinson
  • Separation of composite video signals using dot crawl detector
    Patent number: 7430020
    Abstract: The present invention relates to separation of composite video signals, such as NTSC or PAL signals. In particular, it relates to accurate decoding of chrominance and luminance components, which may reduce so-called dot crawl and false color artifacts of at least some images.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: September 30, 2008
    Assignee: ESS Technology, Inc.
    Inventors: Jordan C. Cookman, Cai-Zhang Zhou
  • Wide dynamic range image sensor and method of use
    Patent number: 7411169
    Abstract: An exemplary image sensor comprises a photodetector proximate to a pixel site, and a light meter proximate to the pixel site configured to approximate an initial charge acquired by the photodetector at the end of a first integration period of a frame exposure period. A reset circuit resets the photodetector if the approximated initial charge acquired by the photodetector exceeds a threshold. A readout circuit detects a final charge acquired by the photodetector at the end of a second integration period of the frame exposure period. If the photodetector was reset, the readout circuit adjusts the final exposure to account for exposure prior to the photodetector having been reset.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: August 12, 2008
    Assignee: ESS Technology, Inc.
    Inventor: Richard A. Mann
  • Method and apparatus for removing electrons from CMOS sensor photodetectors
    Patent number: 7385272
    Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: June 10, 2008
    Assignee: ESS Technology, Inc.
    Inventors: Zeynep Toros, Richard Mann, Selim Bencuya
  • Self-calibrating anti-blooming circuit for CMOS image sensor having a spillover protection performance in response to a spillover condition
    Patent number: 7381936
    Abstract: A method and apparatus to provide blooming protection for a pixel in an array while extending dynamic range.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: June 3, 2008
    Assignee: ESS Technology, Inc.
    Inventors: Mehmet Ali Tan, Jiafu Luo
  • Digital to analog converter calculating a difference between multiple indicators of a multi-bit input signal
    Patent number: 7379006
    Abstract: The present invention relates to multi-bit to pulse width modulated signal conversion, with extensions to digital-to-analog conversion. In particular, it has application to conversion of pulse code modulated signals, such as used in CDs and DVDs, to audio output.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: May 27, 2008
    Assignee: ESS Technology, Inc.
    Inventors: Dustin D. Forman, A. Martin Mallinson, Simon Damphousse
  • Frequency shaping stream signal processor
    Patent number: 7349491
    Abstract: A signal processor has a plurality of channels, each channel configured to receive an input signal stream, to reduce the signal to a direct current signal and to process the signal according to the stream signal. Each channel also has a plurality of low pass filters configured to filter in-phase and quadrature-phase modulator outputs with a first low pass filter and to filter a reference quadrature signals, and a gain control configured to re-modulate gain adjusted output signals with the filtered quadrature signals. The processor further includes an inverter to invert the in-phase filtered reference signal and means to multiply the quadrature gain adjusted output signal.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: March 25, 2008
    Assignee: ESS Technology, Inc.
    Inventor: Andrew Martin Mallinson
  • Asynchronous sample rate converter
    Publication number: 20080068234
    Abstract: Various embodiments perform sample rate conversion of a sample series at an input rate to an output rate. A version of the sample series is corrected with timing error information generated by a digital loop. The digital loop is locked to a first rate and clocked at a second rate.
    Type: Application
    Filed: November 28, 2007
    Publication date: March 20, 2008
    Applicant: ESS Technology, Inc.
    Inventors: Dustin Forman, Andrew Mallinson
  • Method for designing a CMOS sensor using parameters
    Patent number: 7334211
    Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: February 19, 2008
    Assignee: ESS Technology, Inc.
    Inventors: Zeynep Toros, Richard Mann, Selim Bencuya
  • Asynchronous sample rate correction by time domain interpolation
    Patent number: 7330138
    Abstract: A circuit is provided to correct a sample rate by way of time domain interpolation having a first circuit loop having an up/down counter configured to receive an input signal and a feedback signal and an adder configured to receive the output signal from the up/down counter and to output a carry output as the feedback signal to the up/down counter and a second circuit loop configured to transmit a sum output from the adder to a modulator and to feed back an output signal from the modulator to an input of the adder.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: February 12, 2008
    Assignee: ESS Technology, Inc.
    Inventors: Andrew Martin Mallinson, Dustin Forman