Abstract: A color frame identifier circuit generates a pseudo-subcarrier signal and compares the pseudo-subcarrier signal to a sliced color burst of at least one selected line in a video frame. Based on this comparison, a processing circuit determines the color frame.

Abstract: A processing circuit for a sync signal includes a trial circuit and a windowing circuit. The trial circuit includes a counter that generates a count value proportional to the duration between successive sync pulses. When the count value reaches a trial sync spacing count value, a trial window signal is created and the counter is reset. If a predetermined number of subsequent sync pulses occur within the trial window signal, the sync spacing count value is confirmed and stored in a sync spacing register. The windowing circuit includes a counter that generates a count value proportional to the duration between successive window signals, and compares the count value to the value stored in the sync spacing register to generate a window signal. The window signal is compared with the sync signal pass valid sync signals.

Abstract: Transmit amplitude independent adaptive equalizers are provided that compensate for transmission losses in an input signal when the transmit signal amplitude is unknown. Several embodiments are provided, including a first embodiment having an equalizer core, a controllable-swing slicer and an amplitude control loop, a second embodiment having an equalizer core, a fixed-swing slicer and a control loop, a third embodiment having an equalizer core, a variable gain amplifier, and a variable gain amplifier control loop, and a fourth embodiment having an equalizer core, a fixed-swing slicer, a variable gain amplifier, and a variable gain amplifier control loop.

Abstract: In accordance with the teachings described herein, systems and methods are provided for automatically correcting duty cycle distortion. A slicer may be used to receive a data input signal and compare the data input signal with a slicer offset voltage to generate a sliced data signal. The slicer may also receive an offset control signal to automatically adjust the slicer offset voltage. A phase detector may be used to receive the sliced data signal and a recovered clock signal and to compare the sliced data signal with the recovered clock signal to generate a rising edge output signal and a falling edge output signal. The rising edge output signal may correspond to a phase difference between a rising edge of the sliced data signal and an edge of the recovered clock signal. The falling edge output signal may correspond to a phase difference between a falling edge of the sliced data signal and an edge of the recovered clock signal.

Abstract: A remote control for programming a hearing instrument includes a housing and a mechanism associated with the housing for mechanically generating an acoustical pulse for effecting control of a hearing instrument. The remote control is passive. A hearing instrument system includes a hearing instrument having a microphone and programming, and the remote control. The programming is configured to interpret the acoustical pulse generated by the mechanism to effect control of the hearing instrument.

Abstract: In accordance with the teachings described herein, systems and methods are provided for a hearing instrument with self-diagnostics. A detection circuitry may be used to monitor the functional status of at least one transducer by measuring an energy level output of the transducer and comparing the energy level output to a pre-determined threshold level. The detection circuitry may generate an error message output if the measured energy level output of the transducer falls below the pre-determined threshold level. A memory device may be used to store the error message output generated by the detection circuitry.

Abstract: A digital communication system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal.

Abstract: Optical receiver modules are used for receiving high-speed optical data signals. Unfortunately, these optical receiver modules are often tested for the first time after they are packaged in a housing. Thus significant costs are associated with those packaged devices that fail to meet predetermined criteria. An integrated optical receiver module is proposed that has an optical detector direct attached, or flip-chipped or bumped, onto an integrated circuit having an amplifier circuit. The direct attach process is performed when the integrated circuits still reside on a semiconductor wafer prior to dicing thereof. Thus, high speed optical testing of the optical receiver module is possible on a wafer level to determine actual performance characteristics thereof prior to dicing.

Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).

Abstract: In accordance with the teachings described herein, systems and methods are provided for reducing the lock time of a phase locked loop circuit. A phase comparator may be used to detect a phase error between an input reference signal and a feedback clock signal. A frequency synthesizer circuit may be used to control the frequency of an output clock signal as a function of the phase error between the input signal and the feedback clock signal. A feedback divider may be used to divide the frequency of the output clock signal to generate the feedback clock signal. A phase error monitor may be used to detect when the phase error between the input signal and the feedback clock signal reaches a peak value, and in response to detecting the peak value, initialize the feedback divider to reduce the phase error between the input signal and the feedback clock signal.

Abstract: A multi-channel digital hearing instrument is provided that includes a microphone, an analog-to-digital (A/D) converter, a sound processor, a digital-to-analog (D/A) converter and a speaker. The microphone receives an acoustical signal and generates an analog audio signal. The A/D converter converts the analog audio signal into a digital audio signal. The sound processor includes channel processing circuitry that filters the digital audio signal into a plurality of frequency band-limited audio signals and that provides an automatic gain control function that permits quieter sounds to be amplified at a higher gain than louder sounds and may be configured to the dynamic hearing range of a particular hearing instrument user. The D/A converter converts the output from the sound processor into an analog audio output signal. The speaker converts the analog audio output signal into an acoustical output signal that is directed into the ear canal of the hearing instrument user.

Abstract: A tunable ring oscillator, in accordance with the teachings described herein, may include one or more delay circuits having a coarse tuning circuitry and a fine tuning circuitry. The coarse tuning circuitry may be used to set one of a minimum time delay or a maximum time delay as a function of a coarse tuning input. The fine tuning circuitry may be used to adjust between the minimum time delay and the maximum time delay as a function of a fine tuning input.

Abstract: Transmit amplitude independent adaptive equalizers are provided that compensate for transmission losses in an input signal when the transmit signal amplitude is unknown. Several embodiments are provided, including a first embodiment having an equalizer core, a controllable-swing slicer and an amplitude control loop, a second embodiment having an equalizer core, a fixed-swing slicer and a control loop, a third embodiment having an equalizer core, a variable gain amplifier, and a variable gain amplifier control loop, and a fourth embodiment having an equalizer core, a fixed-swing slicer, a variable gain amplifier, and a variable gain amplifier control loop.

Abstract: A reconfigurable processing unit for a digital hearing instrument includes an IS processor module, a plurality of processing units and a crosspoint switch matrix. The IS processor module receives a hearing instrument configuration. Each of the processing modules are configured to process audio signals received by the digital hearing instrument. The crosspoint switch matrix is coupled to the IS processor module and each of the processing modules, and includes at least one crosspoint switch that is configured to route audio signals between processing modules and to combine at least two audio signals. In addition, the IS processor module uses the hearing instrument configuration to program the configuration of the crosspoint switch and thereby control how the crosspoint switch matrix routes and combines audio signals.

Abstract: A digital quasi-RMS detector is provided that approximates the time-varying RMS energy of a signal. The digital quasi-RMS detector rectifies the signal and compares the rectified signal with an estimated present energy value of the audio signal. If the difference between the rectified signal and the estimated present energy value is not greater than zero, then the digital quasi-RMS detector multiplies the rectified signal by a first time constant to generate a first filtered signal and sums the first filtered signal with the estimated present energy value to determine the approximate RMS energy. If the difference between the rectified signal and the estimated present energy is greater than zero, however, then the digital quasi-RMS detector multiplies the rectified signal by a second time constant to generate a second filtered signal and sums the second filtered signal with the estimated present energy value to determine the approximate RMS energy.

Abstract: An adaptive equalizer with a large data rate range is provided. The equalizer comprises an equalizer core, a slicer and an automatic gain control (AGC) loop. The equalizer core is coupled to an input signal from a transmission medium and applies a transfer function to the input signal to compensate for losses incurred in the transmission medium in order to generate a core output signal. The equalizer core is also coupled to a bandwidth control signal that controls a bandwidth of the transfer function. The slicer is coupled to the core output signal and converts the core output signal to a digital output signal having a fixed digital output swing that approximates a transmission swing of the input signal prior to transmission over the transmission medium. The AGC loop is coupled to the core output signal and the digital output signal and compares the core output signal with the digital output signal in order to generate the bandwidth control signal.

Abstract: An adaptive lock position circuit includes a jitter distribution extremity detector and a phase shifting circuit. The jitter distribution extremity detector receives an input data signal and is operable to compare the input data signal with one or more clock signals derived from a recovered clock signal from a clock and data recovery (CDR) circuit to generate one or more control signals that define the boundaries of a jitter extremity detection window. The phase shifting circuit is coupled in a feedback loop with the jitter distribution extremity detector and receives the one or more control signals from the jitter distribution extremity detector and also receives the recovered clock signal. The phase shifting circuit is operable to shift the phase of the recovered clock signal as a function of the one or more control signals to generate a retiming clock signal such that an edge of the retiming clock signal is interpolated within the jitter extremity detection window.

Abstract: A precision, low jitter oscillator circuit is provided that is particularly well-suited for generating a clock signal in miniature digital systems, such as digital hearing aids. The oscillator includes a plurality of differential inverters configured in a feedback loop to generate an oscillating clock signal. The differential inverters include a capacitive trimming network for adjusting the frequency of the oscillating clock signal and employ resistive loads for minimizing jitter in the clock signal. The components of the oscillator are fabricated in a common silicon process to minimize the size of the oscillator.

Abstract: A method and apparatus for avoiding and or recovering from the latch-up condition in a quantized feedback DC restorer circuit for use in a digital data communication system receiver. An automatic gain control (AGC) circuit controls the level of the received data by comparing the AGC output with a quantized output signal from the DC restorer. A carrier detect circuit detects the presence of data transitions in the quantized output signal, and in the absence of such transitions continuously ramps up the gain of the AGC until such transitions are detected. The carrier detect circuit can be further used to disable, either entirely or partially, the positive feedback path of the DC restorer in the absence of transition in the quantized output signal. The present invention further provides an inherent muting function of the DC restorer output signal in the absence of valid data transitions.