Abstract: An auto-configurable video deserializer with embedded audio support includes a video core, a clock generator and an audio core. The video core receives a serial video signal of an unknown video standard, converts the serial video signal into a parallel video signal, and decodes the parallel video signal to identify the unknown video standard and generate one or more auto-configuration signals. The clock generator generates an audio clock signal. The audio core is coupled to the video core and the clock generator, and receives the parallel video signal and one or more auto-configuration signals from the video core and receives the audio clock signal from the clock generator. The audio core uses the auto-configuration signal(s) to automatically locate and extract audio data from within ancillary space of the parallel video signal and synchronizes the extracted audio data with the audio clock signal to generate an audio output signal.

Abstract: A video processing system and method are provided for generating clock and timing signals from an incoming video signal. The system includes a timing reference circuit for generating a reference clock signal, a video format detector coupled to the reference clock signal and to synchronization data derived from the incoming video signal for generating a format signal indicating the format of the incoming video signal, and a clock and timing generator circuit coupled to the format signal and the reference clock signal for generating clock and timing signals that emulate the incoming video signal, and may be locked to the incoming video signal.

Abstract: Transmit amplitude independent adaptive equalizers are provided that compensate for transmission losses in an input signal when the transmit signal amplitude is unknown. Several embodiments are provided, including a first embodiment having an equalizer core, a controllable-swing slicer and an amplitude control loop, a second embodiment having an equalizer core, a fixed-swing slicer and a control loop, a third embodiment having an equalizer core, a variable gain amplifier, and a variable gain amplifier control loop, and a fourth embodiment having an equalizer core, a fixed-swing slicer, a variable gain amplifier, and a variable gain amplifier control loop.

Abstract: A digital hearing aid is provided that includes front and rear microphones, a sound processor, and a speaker. Embodiments of the digital hearing aid include an occlusion subsystem, and a directional processor and headroom expander. The front microphone receives a front microphone acoustical signal and generates a front microphone analog signal. The rear microphone receives a rear microphone acoustical signal and generates a rear microphone analog signal. The front and rear microphone analog signals are converted into the digital domain, and at least the front microphone signal is coupled to the sound processor. The sound processor selectively modifies the signal characteristics and generates a processed signal. The processed signal is coupled to the speaker which converts the signal to an acoustical hearing aid output signal that is directed into the ear canal of the digital hearing aid user.

Abstract: Transimpedance amplifiers (TIAs) are typically used within optical receiver modules to amplify weak photocurrents received from the photodetector, in the form of photodiode, or a PIN diode. Since TIAs are used to amplify weak photocurrents, noise in the resultant amplification of the weak photocurrent is typically a problem. However, TIAs must not only provide low noise amplification of weak photocurrents, but must also operate when a much higher optical power is received by the photodetector and hence a much higher photocurrent is provided to an input port of the TIA. Of course, with the higher photocurrent received from the photodetector the TIA must also exhibit acceptable bit error rate performance as with the lower photocurrents. An elevated front end TIA (EFTIA) is thus provided that offers low noise performance while providing a wide dynamic range, which overcomes the deficiencies of the prior art.

Abstract: A transimpedance amplifier (TIA) circuit and received signal strength indicator (RSSI) circuit are provided on a same integrated circuit substrate for providing of a TIA output signal and a RSSI signal. The RSSI signal is being used as an indication of optical alignment when aligning of an optical fiber to a photodetector coupled with the TIA during optical receiver manufacture or as received optical signal strength during operation. This allows for the TIA and RSSI circuit to be disposed within an optical signal receiver module prior to optical alignment. The TIA overcomes limitations of the prior art by allowing for a 2V reverse bias voltage to be provided on a PIN diode when the PIN diode is used with a single ended 3.3V supply voltage.

Abstract: Transimpedance amplifiers (TIAs) are typically used within optical receiver modules to amplify weak photocurrents received from the photodetector. The TIA amplifies this weak photocurrent into an output voltage that is further provided to other stages of the optical receiver module. Since TIAs are used to amplify weak photocurrents, noise in the resultant amplification of the weak photocurrent is typically a problem. However, TIAs must not only provide low noise amplification of weak photocurrents, but must also operate when a much higher optical power is received by the photodetector and hence a much higher photocurrent is provided to an input port of the TIA. An elevated front end TIA (EFTIA) is thus provided that offers low noise performance while providing a wide dynamic range, which overcomes the deficiencies of the prior art. Furthermore, the EFTIA is provided absent a transistor switching circuit.

Abstract: An equalizer circuit for equalizing first and second differential input signals comprises a differential pair, a reactive load, and first and second input followers. The differential pair defines first and second input nodes and first and second output nodes, and the reactive load is coupled to the differential pair. The first input follower circuit is connected to the first input node of the differential pair and is operable to receive the first differential input signal and to receive a first feedback signal from the differential pair and in response to generate a first input signal at the first input node of the differential pair. The second input follower circuit is connected to the second input node of the differential pair and is operable to receive the second differential input signal and to receive a second feedback signal from the differential pair and in response to generate a second input signal at the second input node of the differential pair.

Abstract: An improved reclocker circuit and router cell are provided that are particularly useful when configured into a router matrix comprising a plurality of interconnected router cells. The improved reclocker circuit includes an integral N-to-1 multiplexer (MUX), wherein N is at least three. The improved router cell includes the reclocker/MUX circuit, a switch, and a fan-out circuit. A plurality of ports are coupled to the router cell circuitry, including an input port, an output port, a plurality of expansion input ports, and a plurality of expansion output ports. The improved router cell couples either the input port or one the expansion input ports to its output port, and it also couples the input port to each of the expansion output ports. By using the improved router cells in the design of a router matrix, jitter induced by the reclocker circuits is minimized.

Abstract: A system for dynamically trimming a voltage controlled oscillator operable to receive a trim signal for adjusting a voltage-to-frequency operating characteristic of the voltage controlled oscillator and receive a tune signal to generate an output signal having an output frequency determined by the voltage-to-frequency operating characteristic includes a trim circuit operable to receive the tune signal and generate the trim signal and increment or decrement the trim signal and condition a change in the trim signal during the increment or decrement so that the voltage-to-frequency operating characteristic of the voltage controlled oscillator drifts from a first voltage-to-frequency operating characteristic to a second voltage-to-frequency operating characteristic.

Abstract: A method of fabricating a solder bumped substrate for a flip-chip integrated circuit (IC) package is provided. The method includes the following steps. Providing a substrate material. Patterning a conductive layer on the substrate material that includes a plurality of circuit traces coupled to a plurality of bonding pads, wherein the bonding pads are arranged to correspond to input/output (I/O) pads on the flip-chip IC. Fabricating a solder mask layer over the conductive layer, wherein the solder mask layer defines a pad opening corresponding to each of the bonding pads, and wherein the pad openings defined by the solder mask layer are tapered such that each pad opening includes an expanded end and a tapered end. Printing solder onto a portion of each bonding pad that is exposed by the expanded end of the corresponding pad opening. Reflowing the printed solder to form solder bumps on each bonding pad.

Abstract: An EEPROM memory cell comprising a transistor on a first conductivity type semiconductor substrate and a capacitor formed on a second conductivity type semiconductor substrate. The capacitor comprises first and second injector regions of third conductivity type, a channel region of second conductivity type separating the first and second injector regions and a first electrically floating structure disposed above the channel region, wherein a first edge portion of the floating structure overlaps a portion of the first injector region and a second edge portion of the first floating structure overlaps a portion of the second injector region, and a control gate region of fourth conductivity type located within the second conductivity type semiconductor substrate region. The gate structure and first floating structure are electrically connected together. In different aspects of the present invention, the EEPROM memory cell may also include a second capacitor.

Abstract: An EEPROM memory cell comprising a transistor on a first conductivity type semiconductor substrate and a capacitor formed on a second conductivity type semiconductor substrate. The capacitor comprises first and second injector regions of third conductivity type, a channel region of second conductivity type separating the first and second injector regions and a first electrically floating structure disposed above the channel region, wherein a first edge portion of the floating structure overlaps a portion of the first injector region and a second edge portion of the first floating structure overlaps a portion of the second injector region, and a control gate region of fourth conductivity type located within the second conductivity type semiconductor substrate region. The gate structure and first floating structure are electrically connected together. In different aspects of the present invention, the EEPROM memory cell may also include a second capacitor.

Abstract: A precision, low jitter oscillator circuit is provided that is particularly well-suited for generating a clock signal in miniature digital systems, such as digital hearing aids. The oscillator includes a plurality of differential inverters configured in a feedback loop to generate an oscillating clock signal. The differential inverters include a capacitive trimming network for adjusting the frequency of the oscillating clock signal and employ resistive loads for minimizing jitter in the clock signal. The components of the oscillator are fabricated in a common silicon process to minimize the size of the oscillator.

Abstract: An EEPROM memory cell comprising a transistor on a first conductivity type semiconductor substrate and a capacitor formed on a second conductivity type semiconductor substrate. The capacitor comprises first and second injector regions of third conductivity type, a channel region of second conductivity type separating the first and second injector regions and a first electrically floating structure disposed above the channel region, wherein a first edge portion of the floating structure overlaps a portion of the first injector region and a second edge portion of the first floating structure overlaps a portion of the second injector region, and a control gate region of fourth conductivity type located within the second conductivity type semiconductor substrate region. The gate structure and first floating structure are electrically connected together. In different aspects of the present invention, the EEPROM memory cell may also include a second capacitor.

Abstract: A non-linear phase detector includes a retiming stage and a phase synchronization stage. The retiming stage is coupled to a data signal and a recovered clock signal. The retiming stage is triggered by the recovered clock signal and samples the data signal to generate a retimed data signal and a clock synchronization signal. The phase synchronization stage is coupled to the retimed data signal and the clock synchronization signal. The phase synchronization stage is triggered by the retimed data signal and samples the clock synchronization signal to generate a phase control signal.

Abstract: A thick film circuit with a perimeter anchored thick film pad is provided. The thick film circuit includes a base substrate, a thick film bonding pad, and a solder mask layer. The thick film bonding pad is formed on the surface of the base substrate. The solder mask layer is also formed on the surface of the base substrate, and overlaps a portion of the thick film bonding pad in order to improve adhesion between the thick film bonding pad and the base substrate.

Abstract: A capacitive device formed on a substrate is provided that comprises a first set of terminals and a second set of terminals. The first set of terminals comprises a positive input terminal and a negative input terminal. The second set of terminals comprises a positive output terminal and a negative output terminal. The capacitor structure further comprises a first film electrode layer disposed above the substrate and having an input side and an output side, the input side having means for providing a coupling location for the negative input terminal, the output side having means for providing a coupling location for the negative output terminal. The capacitor structure further comprises a second film electrode layer also disposed above the substrate and having an input side and an output side, the input side having means for providing a coupling location for the positive input terminal, the output side having means for providing a coupling location for the positive output terminal.

Abstract: A serial digital data communications receiver with an improved automatic cable equalizer that is less susceptible to jitter and has greater multi-standards capability, and an improved automatic gain control system with a DC restorer that provides optimal edge jitter performance while avoiding the possibility of a latch-up condition at the start of data transmission. The automatic cable equalizer for equalizing signals received over cables of different lengths has multiple stages each having a transfer function of 1+Ki[fi(j&ohgr;)] wherein each of the Ki vary in accordance with a sequential gain control methodology. The AGC system uses the difference between band-pass filtered versions of the amplitudes of the input and output of a DC restorer based on quantized feedback, to regulate the AGC circuit.