Abstract: A method and apparatus for avoiding and or recovering from the latch-up condition in a quantized feedback DC restorer circuit for use in a digital data communication system receiver. An automatic gain control (AGC) circuit controls the level of the received data by comparing the AGC output with a quantized output signal from the DC restorer. A carrier detect circuit detects the presence of data transitions in the quantized output signal, and in the absence of such transitions continuously ramps up the gain of the AGC until such transitions are detected. The carrier detect circuit can be further used to disable, either entirely or partially, the positive feedback path of the DC restorer in the absence of transition in the quantized output signal. The present invention further provides an inherent muting function of the DC restorer output signal in the absence of valid data transitions.

Abstract: A multi-layer distributed capacitor structure comprises a bottom electrode layer overlying a monolithic substrate, intermediate pairs of layers of film electrode and dielectric material overlying the bottom electrode, and a top pair of layers of a film electrode and dielectric material overlying the intermediate pairs. The structure contains multiple openings, each opening extending from the top pair of layers through the intermediate layers and optionally through said bottom electrode. Each electrode layer also extends laterally beyond and around the entire periphery of the layers positioned above such that the electrode layers bordering on each opening has edges running along the perimeter of the opening which are left exposed for electrical connection to a circuit using wire interconnects.

Abstract: A serial digital data communications receiver with an improved automatic cable equalizer that is less susceptible to jitter and has greater multi-standards capability, and an improved automatic gain control system with a DC restorer that provides optimal edge jitter performance while avoiding the possibility of a latch-up condition at the start of data transmission. The automatic cable equalizer for equalizing signals received over cables of different lengths has multiple stages each having a transfer function of 1+Ki[fi(j)] wherein each of the Ki vary in accordance with a sequential gain control methodology. The AGC system uses the difference between band-pass filtered versions of the amplitudes of the input and output of a DC restorer based on quantized feedback, to regulate the AGC circuit.

Abstract: A cable driver is disclosed which provides a substantially linear output signal corresponding to an input signal received by the cable driver on a transmission line. The cable driver includes a number of switches coupled by delay elements with cause the switches to operate in a sequential order in response to an input signal. Each of the switches couples an associated current source to an output port, producing a substantially linear output signal on a transmission line connected to the output port. The substantially linearity of the output signal increases the rate at which data may be transmitted over the transmission line, while permitting the rise and fall time of a specified portion of the output signal to be controlled to ensure that electro-magnetic interference is not produced.

Abstract: An improved antifuse which employs the base-emitter junction of a silicided single polysilicon bipolar transistor. The distance between the base metal and emitter metal is shortened and results from self aligning process steps rather than lithographic steps, resulting in a lower and better controlled programming voltage, programming energy and ON state resistance. Typically the conductive filament formed in the new antifuse is about 0.65 microns long and is formed by a voltage pulse having a relatively slow rise time (e.g. 150 microseconds), resulting in improved properties which provide advantages in circuit design and in manufacturing circuits using the new antifuse.

Abstract: A relaxation oscillator, such as a voltage controlled oscillator (VCO), with automatic swing control feedback which dynamically monitors the voltage swing across a capacitor and adjusts the oscillator threshold voltage, at which reversal of the polarity of the charging/discharging current occurs, to maintain the effective voltage swing at a constant level. The improved relaxation oscillator provides a very wide linear range of frequency variation versus control voltage (or current) and allows for the extendibility of linear operation to or near the maximum frequency that can be practically achieved by the oscillator circuitry.

Abstract: A symmetrical clamp clamps the input video signal to a reference voltage during composite sync pulses, so the coupling capacitor discharge current is kept small between composite sync pulses. For startup, the non-symmetrical clamp employs an operational amplifier, diode and controllable current source to charge the coupling capacitor to a minimum desired level, and to discharge the capacitor e.g. when there is a change in DC level so that the output level is too high. A sync slicing detector is also provided, using two comparators. One comparator compares the slicing level with the clamped video and produces a properly sliced composite sync output, while the other compares the clamped video with a small reference voltage and produces a fixed sync output. If the clamped video level drops suddenly, a delayed version of the fixed composite sync output clocks a flip flop, creating a fault signal which discharges a memory capacitor over a time period.

Abstract: A multi-chip module (MCM) assembly has three stacked integrated circuit (IC) layers. The first IC layer is electrically flip-chip connected to a substrate. The back of the second IC layer may be glued to the back of the first IC layer, and the second and third IC layers are electrically flip-chip connected to each other. In one embodiment, the third IC layer is electrically connected to the substrate through a vertical interconnect element for high circuit density. In another, the second IC layer is electrically connected to the substrate using wire bonding for greater post-fabrication customization flexibility. In still another embodiment, the MCM assembly comprises two stacked IC layers where the second IC layer is electrically flip-chip connected to the first IC layer and the second layer is electrically connected to the substrate through a vertical interconnect element.

Abstract: A system of resistive end termination and transmission line routing is disclosed for matching the impedance of an IC load to that of a signal source and a transmission line. Each integrated circuit has an internal termination resistor designed to match the characteristic impedance of the transmission line and preferably also the impedance of the source. When the source drives multiple IC devices on a printed circuit board, the devices are cascaded in a chain with the internal resistors of all but the last IC device in the chain bypassed by a short circuit underneath the device, so that a continuous transmission line is provided to the last IC device. The last IC in the chain, which does not have a short circuit underneath it, provides the necessary resistive termination by simply connecting the appropriate pin to a common reference in the circuit. The invention is also applicable to differential applications in which first and second complementary signal sources feed each IC device.

Abstract: An improved phase detector for detecting the difference between an information signal and a clock signal is provided. The information signal is divided into a plurality of N divided signals, the data rate of each divided signal being the data rate of the information signal divided by N. A plurality of N variable width difference pulse signals are generated each being responsive to the phase difference between a divided signal and the clock signal. One or more fixed width reference pulse signals having a width proportional to one-half clock period are also generated. A phase error signal is then provided in response to the N difference pulse signals and the one or more reference pulse signals. Preferably, N is equal to 2.sup.M, where M is a positive integer greater than or equal to one.

Abstract: Sync separator and video detector circuits, including a sync tip clamp having symmetrical and non-symmetrical clamps. The symmetrical clamp clamps the input video signal to a reference voltage during composite sync pulses, so the coupling capacitor discharge current is kept small between composite sync pulses. For startup, the non-symmetrical clamp employs an operational amplifier, diode and controllable current source to charge the coupling capacitor to a minimum desired level, and to discharge the capacitor e.g. when there is a change in DC level so that the output level is too high. A sync slicing detector is also provided, using two comparators. One comparator compares the slicing level with the clamped video and produces a properly sliced composite sync output, while the other compares the clamped video with a small reference voltage and produces a fixed sync output.

Abstract: An improved antifuse which employs the base-emitter junction of a silicided single polysilicon bipolar transistor. The distance between the base metal and emitter metal is shortened and results from self aligning process steps rather than lithographic steps, resulting in a lower and better controlled programming voltage, programming energy and ON state resistance. Typically the conductive filament formed in the new antifuse is about 0.65 microns long and is formed by a voltage pulse having a relatively slow rise time (e.g. 150 microseconds), resulting in improved properties which provide advantages in circuit design and in manufacturing circuits using the new antifuse.

Abstract: A multi-channel synchronous compander for hearing aids, in which the input signal from an input transducer is directed through a 2:1 front compressor, then through a band splitting filter to divide it into a desired number of frequency bands, then through expander/compressors to provide selected expansion/compression of each frequency band depending on the user's hearing impairment. The outputs of the expander/compressors are summed, amplified and directed to the hearing aid output transducer. The compressor and each expander/compressor are all controlled by control signals derived from the compressed signal level at the output of the front compressor. The use of common control signals for both the front end compression and the expansion removes the need for close matching of temporal performance and improves the output signal fidelity. The front compressor allows the filter capacitors to be reduced in size so that they can be integrated.

Abstract: A multi-layer film capacitor structure has a bottom electrode layer on a monolithic substrate, intermediate pairs of layers of film electrode and dielectric material overlying the bottom electrode, and a top pair of layers of a film electrode and film dielectric overlying the intermediate pairs. The structure preferably has a mesa configuration, in which each electrode layer extends laterally beyond the periphery of the layers above it around the entire periphery of the device. Each electrode layer therefore has a top surface which is accessible at its projecting edge through a via, so that the electrodes can be accessed in any combination to permit any desired circuit connection. If desired the dielectric materials can have different frequency characteristics, allowing a single capacitor structure to be optimized for a filter. Either the bottom electrode or the top electrode or both can be grounded and capacitor connections can be made to intermediate layers, to reduce parasitic capacitance effects.

Abstract: A control circuit for use with a phase locked loop in a digital video receiver. The digital receiver accepts a serial digital input signal which can comprise composite or component video signals. The phase locked loop comprises a phase detector, a loop filter, and a voltage controlled oscillator (VCO) and includes a divide-by-two modulus divider coupled to the output of the VCO. The VCO has an oscillation frequency control port and the divider has a frequency select port. The control circuit includes an automatic fine tuning and frequency sweeping stage which is coupled to the output of the loop filter and the oscillation frequency control port. The tuning and frequency stage provides temperature drift correction for the VCO. In addition, the tuning and frequency stage "sweeps" the oscillation frequency of the VCO to aid in "locking" the phase locked loop to the phase or frequency of the input signal. Once locked, timing signals and digital data can be extracted from the input signal.

Abstract: A method and a structure for reducing the stresses arising in a hybrid circuit from the interface between the encapsulant and the substrate. An additional layer, preferably of the same material as the substrate, is added to the outside surface of the encapsulant. The purpose of the layer is to provide a second opposing surface to balance and thereby reduce the stress originating from the encapsulant/substrate interface. The second layer is applied prior to the curing of the encapsulant material.

Abstract: To encapsulate IC chips or other parts located in openings in a tape carrier, upper and lower mold halves are closed forming a cavity about each chip. The lower mold half has a lower mold part containing a lower cavity half, and a front wall extending down to a runner groove. A slide normally covers the runner groove and contains runner channels leading to a small side gate in each cavity, without any plastic contacting the tape. After molding the upper mold half is raised and ejector pins push the molded parts with it, away from the lower mold half, performing auto degating. The molded parts are then ejected from the upper mold half, the slide is retracted and the plastic in the runner system is ejected. This allows reel to reel encapsulation of chips or other parts on a tape.

Abstract: A self-adjusting window circuit suitable for fabrication as a monolithic integrated circuit. The self-adjusting window circuit comprises an input port, a positive edge detector coupled to the input port, a latch coupled to the output of the edge detector and a charging stage coupled to the latch. The input signal comprises a signal having a sequence of pulses appearing at a predetermined scan rate, for example, a composite video signal. The input port feeds the input signal to the edge detector which produces a pulse output signal in response to detecting a pulse in the input signal. The pulse output from the edge detector is latched and used to generate a charging control signal which controls the charging stage. In response to the charging control signal, the charging stage produces a window control signal for a predetermined period.

Abstract: A device for restoring DC and non-zero average components of a serially transmitted binary signal which has been AC coupled. The device comprises an input port for the binary signal, a clamping circuit, a feedback network, a summing node, and an output port. The input port includes a capacitor for coupling the binary signal to the summing node and the clamping circuit. The feedback network includes an input and an output which are also connected to the summing node. The clamping circuit clamps the positive and negative peaks of the AC coupled binary signal which exceed a predetermined range. The feedback network latches the AC coupled binary signal and produces a current signal. For a binary signal which is within the predetermined range, the clamping circuit exhibits a very high input impedance, thereby causing the current signal to charge the coupling capacitor and produce a voltage which is added to the AC coupled binary signal at the summing node.

Abstract: An improved differential gain stage for a bipolar monolithic integrated circuit. The integrated circuit is formed from a semiconductor substrate, and the differential gain stage includes first and second bipolar transistors. The base of the first transistor and the base of the second transistor form a differential input for the gain stage comprising non-inverting and inverting inputs respectively. The collectors of the transistors form a differential output. The differential gain stage includes a capacitor stage comprising: a peaking capacitor, and first, second, third and fourth capacitor structures. The peaking capacitor is coupled between the emitters of the first and second transistors. The first and second capacitor structures are located at a first spaced relationship from the substrate and the first capacitor is coupled to the emitter of the first transistor and the second capacitor is coupled to the emitter of the second transistor.