Abstract: A high electron mobility transistor epitaxial structure includes a substrate, a nucleation layer, a buffer layer, a first nitride layer, a second nitride layer, a channel layer, and a barrier layer. The nucleation layer is located above the substrate. The buffer layer is located above the nucleation layer. The first nitride layer is located above the buffer layer and is in contact with the buffer layer. The second nitride layer is located above the first nitride layer and is in contact with the first nitride layer. A film thickness of the first nitride layer is less than a film thickness of the second nitride layer. The second nitride layer is carbon doped. A carbon concentration of the first nitride layer is less than a carbon concentration of the second nitride layer. The channel layer is located above the second nitride layer.

Abstract: A method for epitaxy of a high electron mobility transistor includes: provide a substrate; form a nucleation layer on the substrate; form a buffer layer on the nucleation layer; form a first nitride layer being in contact with the buffer layer on the buffer layer; form a second nitride layer being in contact with the first nitride layer on the first nitride layer, and perform carbon doping on the second nitride layer; form a channel layer on the second nitride layer; and form a barrier layer on the channel layer; a two-dimensional electron gas is formed in the channel layer along an interface between the channel layer and the barrier layer; a growth temperature of the second nitride layer is less than a growth temperature of the first nitride layer; a film thickness of the first nitride layer is less than a film thickness of the second nitride layer.

Abstract: A light-emitting element structure includes a substrate, a nucleation layer located above the substrate, a buffer layer located above the nucleation layer, a first nitride layer located above the buffer layer and being in contact with the buffer layer, a second nitride layer located above the first nitride layer and being in contact with the first nitride layer, a first semiconductor layer located above the second nitride layer, a light-emitting layer, and a second semiconductor layer located above the light-emitting layer. A film thickness of the first nitride layer is smaller than a film thickness of the second nitride layer. A dislocation defect density of the second nitride layer is smaller than or equal to 3×109 cm?2. The light-emitting layer is located above the first semiconductor layer and is adapted to emit light when electrons and holes recombine.

Abstract: A method of manufacturing a light-emitting element, including: provide a substrate; form a nucleation layer above the substrate; form a buffer layer above the nucleation layer; form a first nitride layer being in contact with the buffer layer above the buffer layer; form a second nitride layer being in contact with the first nitride layer above the first nitride layer; form a first semiconductor layer above the second nitride layer; form a light-emitting layer above the first semiconductor layer; form a second semiconductor layer above the light-emitting layer. The light-emitting layer is adapted to emit light when electrons and holes recombine. A film thickness of the first nitride layer is smaller than a film thickness of the second nitride layer, and a growth pressure of the first nitride layer is smaller than a growth pressure of the second nitride layer.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A semiconductor substrate and a method of manufacturing the same are provided. The method includes epitaxially growing a buffer layer and a silicon carbide layer on a silicon surface of an N-type silicon carbide substrate, and the silicon carbide layer is high-resistivity silicon carbide or N-type silicon carbide (N—SiC). Next, a gallium nitride epitaxial layer is epitaxially grown on the silicon carbide layer to obtain a semiconductor structure composed of the buffer layer, the silicon carbide layer, and the gallium nitride epitaxial layer. After the epitaxial growth of the gallium nitride epitaxial layer, a laser is used to form a damaged layer in the semiconductor structure, and a chip carrier is bonded to the surface of the gallium nitride epitaxial layer, and then the N-type silicon carbide and the semiconductor structure are separated at the location of the damaged layer.

Abstract: Ingot puller apparatus for preparing a single crystal silicon ingot by the Czochralski method are disclosed. The ingot puller apparatus includes a heat shield. The heat shield has a leg segment that includes a void (i.e., an open space without insulation) disposed in the leg segment. The heat shield may also include insulation partially within the heat shield.

Abstract: A method for producing a silicon ingot by the horizontal magnetic field Czochralski method includes rotating a crucible containing a silicon melt, applying a horizontal magnetic field to the crucible, contacting the silicon melt with a seed crystal, and withdrawing the seed crystal from the silicon melt while rotating the crucible to form a silicon ingot. The crucible has a wettable surface with a cristobalite layer formed thereon.

Abstract: A crystal growing method for crystals include the following steps. A first crystal seed is provided, the first crystal seed has a first monocrystalline proportion and a first size. N times of crystal growth processes are performed on the first crystal seed, wherein each of the crystal growth process will increase the monocrystalline proportion, and the N times of crystal growth processes are performed until a second crystal having a monocrystalline proportion of 100% is reached, and wherein the N times includes more than 3 times of crystal growth processes. Each crystal growth process includes adjusting a ratio difference (?Tz/?Tx) between an axial temperature gradient (?Tz) and a radial temperature gradient (?Tx) of the crystal, so as to control the ratio difference within a range of 0.5 to 3 for forming the second crystal.

Abstract: A silicon carbide crystal and a silicon carbide wafer, wherein a monocrystalline proportion of the silicon carbide crystal and the silicon carbide wafer is 100%, the resistivity thereof is in a range of 15 m?·cm to 20 m?·cm, and a deviation of an uniformity of the resistivity thereof is less than 0.4%.

Abstract: A method of growing the silicon carbide crystal includes the following steps. A raw material containing a carbon element and a silicon element, and a seed crystal located above the raw material are provided in a reactor. A growth process of the silicon carbide crystal is performed, wherein the growth process includes heating the reactor and the raw material to form silicon carbide crystal on the seed crystal. In the growth process, a ratio difference (?Tz/?Tx) between an axial temperature gradient (?Tz) and a radial temperature gradient (?Tx) of the silicon carbide crystal is adjusted so that the ratio difference is controlled in the range of 0.5 to 3 to form the silicon carbide crystal. The silicon carbide crystal formed by the above growth method can have a uniform resistivity distribution and excellent geometric performance.

Abstract: A crystal growth method, including providing a seed crystal in a crystal growth furnace, and forming a crystal on the seed crystal along a first direction after multiple time points, is provided. The crystal includes multiple sub-crystals stacked along the first direction, a corresponding one of the sub-crystals is formed at each of the time points, and the sub-crystals include multiple end surfaces away from the seed crystal, so that a difference value of maximum temperatures of any two of the end surfaces is less than or equal to 20 degrees. A wafer is also provided.

Abstract: A crystal growth furnace system, including an external heating module, a furnace, a first driven device, a second driven device, and a control device, is provided. The furnace is movably disposed in the external heating module. The first driven device drives the furnace to move along an axis. The second driven device drives the furnace to rotate around the axis. The control device is electrically connected to the first driven device, the second driven device, and the external heating module.

Abstract: A method for doping a single crystal silicon ingot pulled includes heating a vaporization cup. The method also includes maintaining a pressure of an interior of the housing at a first pressure. The method further includes injecting liquid dopant into the dopant injection tube and the vaporization cup. A pressure of the liquid dopant is maintained at a second pressure greater than the first pressure prior to injection into the dopant injection tube and the vaporization cup. The method also includes vaporizing the liquid dopant into vaporized dopant within the housing. The liquid dopant is vaporized by flash evaporation by heating the liquid dopant with the vaporization cup and reducing the pressure of the liquid dopant from the second pressure to the first pressure by injecting the liquid dopant into the housing. The method further includes channeling the vaporized dopant into the housing using the dopant injection tube.

Abstract: Methods for growing single crystal silicon ingots that involve silicon feed tube inert gas control are disclosed. Ingot puller apparatus that include a flange that extends radially from a silicon funnel or from a silicon feed tube to reduce backflow of gases from the silicon feed tube into the growth chamber are also disclosed.

Abstract: A manufacturing method of a silicon carbide ingot includes the following. A raw material containing carbon and silicon and a seed located above the raw material are provided in a reactor. A first surface of the seed faces the raw material. The reactor and the raw material are heated, where part of the raw material is vaporized and transferred to the first surface of the seed and a sidewall of the seed and forms a silicon carbide material on the seed, to form a growing body containing the seed and the silicon carbide material. The growing body grows along a radial direction of the seed, and the growing body grows along a direction perpendicular to the first surface of the seed. The reactor and the raw material are cooled to obtain a silicon carbide ingot. A diameter of the silicon carbide ingot is greater than a diameter of the seed.

Abstract: A material analysis method is provided. A plurality of wafers processed from a plurality of ingots are measured by a measuring instrument to obtain an average of a bow of each of the wafers processed from the ingots and a plurality of full widths at half maximum (FWHM) of each of the wafers. Key factors respectively corresponding to the ingots are calculated according to the FWHM of the wafers. A regression equation is obtained according to the key factors and the average of the bows.

Abstract: The disclosure provides a wafer inspection method and wafer inspection apparatus. The method includes: receive scanning information of at least one wafer, wherein the scanning information includes a plurality of haze values; the scanning information is divided into a plurality of information blocks according to the unit block, and the feature value of each of the plurality of information blocks is calculated according to the plurality of haze values included in each of the plurality of information blocks; and converting the feature value into a color value according to the haze upper threshold and the haze lower threshold, generating the color value corresponding to the at least one wafer according to the converted color value according to the feature value, whereby the color graph displays the texture content of the at least one wafer.

Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a step of high pressure bonding.

Abstract: A computer device includes at least one processor in communication with at least one memory device. The at least one processor is programmed to store, in the at least one memory device, a model for simulating a portion of an assembly line and receive scan data of a first inspection of a product being assembled, execute the model using the scan data as inputs to generate a final profile of the product, compare the final profile to one or more thresholds, determine if the final profile exceeds at least one of the one or more thresholds, and adjust the first device if the determination is that the final profile exceeds at least one of the one or more thresholds.