Patents Assigned to GLOBALWAFERS CO., LTD.
  • High resistivity single crystal silicon ingot and wafer having improved mechanical strength
    Patent number: 11655559
    Abstract: A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×1014 atoms/cm3 and/or germanium at a concentration of at least about 1×1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: May 23, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Soubir Basak, Igor Peidous, Carissima Marie Hudson, HyungMin Lee, ByungChun Kim, Robert J. Falster
  • High resistivity single crystal silicon ingot and wafer having improved mechanical strength
    Patent number: 11655560
    Abstract: A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×1014 atoms/cm3 and/or germanium at a concentration of at least about 1×1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: May 23, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Soubir Basak, Igor Peidous, Carissima Marie Hudson, Hyungmin Lee, Byungchun Kim, Robert J. Falster
  • SEMICONDUCTOR EPITAXY STRUCTURE
    Publication number: 20230138899
    Abstract: A semiconductor epitaxy structure includes a silicon carbide substrate, a nucleation layer, a gallium nitride buffer layer, and a stacked structure. The nucleation layer is formed on the silicon carbide substrate, the gallium nitride buffer layer is disposed on the nucleation layer, and the stacked structure is formed between the nucleation layer and the gallium nitride buffer layer. The stacked structure includes: a plurality of silicon nitride (SiNx) layers and a plurality of aluminum gallium nitride (AlxGa1-xN) layers alternately stacked, wherein the first layer of the plurality of silicon nitride layers is in direct contact with the nucleation layer.
    Type: Application
    Filed: May 30, 2022
    Publication date: May 4, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Tzu-Yao Lin, Jia-Zhe Liu, Ying-Ru Shih
  • METHOD FOR CALCULATING OBJECT PICK-AND-PLACE SEQUENCE AND ELECTRONIC APPARATUS FOR AUTOMATIC STORAGE PICK-AND-PLACE
    Publication number: 20230126461
    Abstract: A method for calculating an object pick-and-place sequence and an electronic apparatus for automatic storage pick-and-place are provided. When a warehousing operation is to be performed, the following steps are performed. A weight of an object to be stocked that is to be put on a shelf is obtained. The weight is substituted into a plurality of coordinate positions corresponding to a plurality of unused grid positions respectively, so as to calculate a plurality of estimated center of gravity positions. Whether the estimated center of gravity positions are located within a balance standard area is determined so as to sieve out a plurality of candidate grid positions from these unused grid positions. One of the candidate grid positions is selected as a recommended position of the object to be stocked.
    Type: Application
    Filed: July 13, 2022
    Publication date: April 27, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Chia-Lin Li, Shang-Chi Wang, Chi Yuan Hsu, Han-Zong Wu
  • WAFER JIG, WAFER STRUCTURE AND WAFER PROCESSING METHOD
    Publication number: 20230126487
    Abstract: Provided is a wafer jig including a bottom wall and a ring-shaped side wall. The bottom wall has a supporting surface. The ring-shaped side wall is connected to a periphery of the bottom wall. The ring-shaped side wall includes at least two step portions. The two step portions include a first step portion and a second step portion. The first step portion is connected between the supporting surface and the second step portion, and the first step portion protrudes along a direction toward a center of the bottom wall. The ring-shaped side wall surrounds the center. In addition, a wafer structure and a wafer processing method are also provided.
    Type: Application
    Filed: July 6, 2022
    Publication date: April 27, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Chan-Ju Wen, Chia-Chi Tsai, Han-Zong Wu
  • Radio frequency silicon on insulator structure with superior performance, stability, and manufacturability
    Patent number: 11626318
    Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: April 11, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Michael R. Seacrist, Robert W. Standley, Jeffrey L. Libbert, Hariprasad Sreedharamurthy, Leif Jensen
  • CVD apparatus
    Patent number: 11598021
    Abstract: A preheat ring (126) for use in a chemical vapor deposition system includes a first portion and a second portion selectively coupled to the first portion such that the first and second portions combine to form an opening configured to receive a susceptor therein. Each of the first and second portions is independently moveable with respect to each other.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: March 7, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Shawn George Thomas, Gang Wang
  • METHOD FOR IDENTIFYING WAFER
    Publication number: 20230064159
    Abstract: A method for identifying a wafer is provided, which includes the following steps. A marked frame is obtained from a wafer inspection picture. A gray scale index corresponding to the marked frame is calculated based on a gray scale value corresponding to each of multiple pixels included in the marked frame. The gray scale index indicates a proportion of pixels whose gray scale values are greater than a specified value. Whether a trace pattern in the marked frame is a scratch or a grain boundary is determined based on the gray scale index.
    Type: Application
    Filed: August 3, 2022
    Publication date: March 2, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Shang-Chi Wang, Chia-Jung Lee, Bo-Ting Lin, Chia-Chi Tsai
  • METHOD OF MANUFACTURING SILICON CARBIDE INGOT
    Publication number: 20230067197
    Abstract: The disclosure provides a silicon carbide seed crystal and a method of manufacturing a silicon carbide ingot. The silicon carbide seed crystal has a silicon surface and a carbon surface opposite to the silicon surface. A difference D between a basal plane dislocation density BPD1 of the silicon surface and a basal plane dislocation density BPD2 of the carbon surface satisfies the following formula (1), a local thickness variation (LTV) of the silicon carbide seed crystal is 2.5 ?m or less, and a stacking fault (SF) density of the silicon carbide seed crystal is 10 EA/cm2 or less: D=(BPD1?BPD2)/BPD1?25%??(1).
    Type: Application
    Filed: October 28, 2022
    Publication date: March 2, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventor: Ching-Shan Lin
  • High resistivity SOI wafers and a method of manufacturing thereof
    Patent number: 11594446
    Abstract: A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: February 28, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Srikanth Kommu, Gang Wang, Shawn George Thomas
  • Methods for producing a single crystal silicon ingot using boric acid as a dopant and ingot puller apparatus that use a solid-phase dopant
    Patent number: 11585010
    Abstract: Methods for producing a single crystal silicon ingot are disclosed. The ingot is doped with boron using solid-phase boric acid as the source of boron. Boric acid may be used to counter-dope the ingot during ingot growth. Ingot puller apparatus that use a solid-phase dopant are also disclosed. The solid-phase dopant may be disposed in a receptacle that is moved closer to the surface of the melt or a vaporization unit may be used to produce a dopant gas from the solid-phase dopant.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: February 21, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: William L. Luter, Hariprasad Sreedharamurthy, Stephan Haringer, Richard J. Phillips, Nan Zhang, Yu-Chaio Wu
  • Epitaxial structure
    Patent number: 11588014
    Abstract: An epitaxial structure includes a substrate, a nucleation layer on the substrate, a buffer layer on the nucleation layer, and a nitride layer on the buffer layer. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al(1?x)InxN, where 0?x?1. A maximum value of the x value in the regions decreases along the thickness direction, and the x value in the chemical composition of each two regions consists of a fixed region and a gradient region, wherein a gradient slope of the gradient regions is ?0.1%/nm to ?50%/nm, and a stepwise slope of the fixed regions is ?0.1%/loop to ?50%/loop. A thickness of the nucleation layer is less than that of the buffer layer. A surface roughness of the nucleation layer in contact with the buffer layer is greater than that of the buffer layer in contact with the nitride layer.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: February 21, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen-Lun Huang, Ying-Ru Shih
  • Method of preparing an isolation region in a high resistivity silicon-on-insulator substrate
    Patent number: 11587825
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: February 21, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Jeffrey L. Libbert
  • Epitaxial structure
    Patent number: 11588015
    Abstract: An epitaxial structure includes a substrate, a nucleation layer on the substrate, a buffer layer on the nucleation layer, and a nitride layer on the buffer layer. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al(1-x)InxN, where 0?x?1. A maximum value of the x value in the plurality of regions is the same, a minimum value of the x value in the plurality of regions is the same, and an absolute value of a gradient slope of each of the regions is 0.1%/nm to 50%/nm. A thickness of the nucleation layer is less than a thickness of the buffer layer. A roughness of a surface of the nucleation layer in contact with the buffer layer is greater than a roughness of a surface of the buffer layer in contact with the nitride layer.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: February 21, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen-Lun Huang, Ying-Ru Shih
  • METHOD OF SiC WAFER PROCESSING
    Publication number: 20230052218
    Abstract: Provided is a method of SiC wafer processing, and the method includes the following steps. A SiC wafer is provided, and the SiC wafer has a first surface and an opposing second surface. A fine grinding process is performed on the first surface and the second surface of the SiC wafer. A dry etching process is performed on the first surface and the second surface of the SiC wafer to make the roughness of the first surface and the second surface 2.5 nm or less. After the dry etching process, a polishing process is performed on the first surface and the second surface of the SiC wafer.
    Type: Application
    Filed: July 11, 2022
    Publication date: February 16, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Shih-Che Hung, Wen-Huai Yu, Wen-Ching Hsu
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20230045328
    Abstract: A semiconductor structure includes a substrate, a first nitride layer, a second nitride layer, a third nitride layer, and a polarity inversion layer. The first nitride layer is formed on the substrate, and the polarity inversion layer formed at a surface of the first nitride layer converts a non-metallic polar surface of the first nitride layer into a metallic polar surface of the polarity inversion layer. The second nitride layer is formed on the polarity inversion layer. The third nitride layer is formed on the second nitride layer.
    Type: Application
    Filed: May 26, 2022
    Publication date: February 9, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Po Jung Lin, Tzu-Yao Lin
  • INGOT JIG ASSEMBLY AND INGOT EDGE-POLISHING MACHINE TOOL
    Publication number: 20230038035
    Abstract: An ingot jig assembly is provided, including an end surface clamping jig and an ingot positioning jig. The end surface clamping jig includes two opposite clamping parts. The ingot positioning jig is located below the end surface clamping jig and includes a first base, an adjusting base, and two rollers. The adjusting base is located between the first base and the end surface clamping jig and is movably disposed on the first base along a first axis to be close to or away from the end surface clamping jig. The two rollers are rotatably disposed on the adjusting base. An ingot edge-polishing machine tool is also provided.
    Type: Application
    Filed: July 8, 2022
    Publication date: February 9, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Wan Ti Lin, Tang-Chi Lin
  • WAFER AND MANUFACTURING METHOD OF WAFER
    Publication number: 20230011749
    Abstract: A wafer includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doped regions and a plurality of second doped regions. The first doped regions and the second doped regions are located on a first surface of the semiconductor substrate. The second doped regions contact the first doped regions. The first doped regions and the second doped regions are alternately arranged. Both of the first doped regions and the second doped regions include a plurality of N-type dopants. The doping concentration of the N-type dopants in each of the first doped regions is not greater than the doping concentration of the N-type dopants in each of the second doped regions.
    Type: Application
    Filed: February 14, 2022
    Publication date: January 12, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Chenghan Tsao, Han-Zong Wu
  • WAFER PROCESSING APPARATUS
    Publication number: 20220415674
    Abstract: A wafer processing apparatus includes a pressure applying element, a rotatable element, a control element, and a heat source. The pressure applying element includes a first pressure applying head having a first working surface and a second pressure applying head having a second working surface. The rotatable element and the pressure applying element are connected. The control element is electrically connected to the rotatable element. The heat source is disposed beside the pressure applying element.
    Type: Application
    Filed: April 13, 2022
    Publication date: December 29, 2022
    Applicant: GlobalWafers Co., Ltd.
    Inventor: Hsiu Chi Liang
  • Cleave systems having spring members for cleaving a semiconductor structure and methods for cleaving such structures
    Patent number: 11538698
    Abstract: Cleave systems for cleaving a semiconductor structure are disclosed. The cleave systems may include a cleave arm that is moveable from a starting position to a raised position in which a cleave stress is applied to the semiconductor structure. Spring members store energy as the cleave arm is raised with the stored spring energy causing the structure to cleave into two pieces upon initiation of the cleave across the structure.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: December 27, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventor: Justin Scott Kayser