Abstract: An improved high electron mobility transistor (HEMT) structure includes in order a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer, wherein the buffer layer includes a dopant. The channel layer having a dopant doping concentration less than that of the buffer layer. A two-dimension electron gas is formed in the channel layer along an interface between the channel layer and the barrier layer. A dopant doping concentration of the channel layer at an interface between the channel layer and the barrier layer is equal to or greater than 1×1015 cm?3.

Abstract: An improved high electron mobility transistor (HEMT) structure includes a substrate, a nitride nucleation layer, a nitride buffer layer, a nitride channel layer, and a barrier layer. The nitride buffer layer includes a metal dopant. The nitride channel layer has a metal doping concentration less than that of the nitride buffer layer. A two-dimensional electron gas is formed in the nitride channel layer along an interface between the nitride channel layer and the barrier layer. A metal doping concentration X at an interface between the nitride buffer layer and the nitride channel layer is defined as the number of metal atoms per cubic centimeter, and a thickness Y of the nitride channel later is in microns (?m) and satisfies Y?(0.2171)ln(X)?8.34, thereby reducing an influence of the metal dopant to a sheet resistance value of the nitride channel layer and providing the improved HEMT structure having a better performance.

Abstract: Nitrogen-doped CZ silicon crystal ingots and wafers sliced therefrom are disclosed that provide for post epitaxial thermally treated wafers having oxygen precipitate density and size that are substantially uniformly distributed radially and exhibit the lack of a significant edge effect. Methods for producing such CZ silicon crystal ingots are also provided by controlling the pull rate from molten silicon, the temperature gradient and the nitrogen concentration. Methods for simulating the radial bulk micro defect size distribution, radial bulk micro defect density distribution and oxygen precipitation density distribution of post epitaxial thermally treated wafers sliced from nitrogen-doped CZ silicon crystals are also provided.

Abstract: A slurry sprayer for supplying a slurry to a wire saw during ingot slicing is disclosed. The slurry sprayer includes a main body and a cover plate that is detachable from the main body for cleaning the slurry sprayer. In some embodiments, the slurry sprayer includes an adjustable support that allows the incline angle of the sprayer to be adjusted and allows the vertical and horizontal position of the slurry sprayer to be adjusted. In some embodiments, the slurry sprayer includes two feed openings to allow the slurry pressure to be more equalized across the slurry sprayer.

Abstract: A bonding wafer structure includes a support substrate, a bonding layer, and a silicon carbide (SiC) layer. The bonding layer is formed on a surface of the support substrate, and the SiC layer is bonded onto the bonding layer, in which a carbon surface of the SiC layer is in direct contact with the bonding layer. The SiC layer has a basal plane dislocation (BPD) of 1,000 ea/cm2 to 20,000 ea/cm2, a total thickness variation (TTV) greater than that of the support substrate, and a diameter equal to or less than that of the support substrate. The bonding wafer structure has a TTV of less than 10 ?m, a bow of less than 30 ?m, and a warp of less than 60 ?m.

Abstract: A wafer and a wafer processing method are included. The wafer processing method includes the following steps. A wafer is provided having a first surface and a second surface opposite to the first surface. A fixture pattern is pasted on the first surface to cover a first portion of the first surface of the wafer, and a second portion of the first surface is exposed by the fixture pattern. A first etching step is performed on the second portion of the first surface to form a first etching pattern on the first surface of the wafer. The fixture pattern is removed from the first surface, and the second surface of the wafer is ground.

Abstract: Methods for forming single crystal silicon ingots with improved resistivity control are disclosed. The methods involve growth of a sample rod. The sample rod may have a diameter less than the diameter of the product ingot. The sample rod is cropped to form a center slab. The resistivity of the center slab may be measured directly such as by a four-point probe. The sample rod or optionally the center slab may be annealed in a thermal donor kill cycle prior to measuring the resistivity, and the annealed rod or slab is irradiated with light in order to enhance the relaxation rate and enable more rapid resistivity measurement.

Abstract: A polishing assembly for polishing of silicon wafers includes a polishing pad, a polishing head assembly, a temperature sensor, and a controller. The polishing head assembly holds a silicon wafer to position the silicon wafer in contact with the polishing pad. The polishing head assembly selectively varies a removal profile of the silicon wafer. The temperature sensor collects thermal data from a portion of the polishing pad. The controller is communicatively coupled to the polishing head assembly and the temperature sensor. The controller receives the thermal data from the temperature sensor and operates the polishing head assembly to selectively vary the removal profile of the silicon wafer based at least in part on the thermal data.

Abstract: A mono-crystalline silicon growth apparatus is provided. The mono-crystalline silicon growth apparatus includes a furnace, a support base disposed in the furnace, a crucible disposed on the support base, and a heating module. The support base and the crucible do not rotate relative to the heating module, and an axial direction is defined to be along a central axis of the crucible. The heating module is disposed at an outer periphery of the support base and includes a first heating unit, a second heating unit, and a third heating unit. The first heating unit, the second heating unit, and the third heating unit are respectively disposed at positions with different heights corresponding to the axial direction.

Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.

Abstract: A semiconductor structure, including a substrate, a first nitride layer, a polarity inversion layer, a second nitride layer, and a third nitride layer, is provided. The first nitride layer is located on the substrate. The polarity inversion layer is located on a surface of the first nitride layer to convert a non-metallic polarity surface of the first nitride layer into a metallic polarity surface of the polarity inversion layer. The second nitride layer is located on the polarity inversion layer. The third nitride layer is located on the second nitride layer. The substrate, the first nitride layer, the polarity inversion layer, and the second nitride layer include iron element.

Abstract: An ingot evaluation method and a detecting apparatus are provided. Defect information of a wafer is obtained from an ingot. The defect information includes a position of at least one defect identified by optical detection. A center-of-gravity position of the defect is determined according to the defect information. Uniformity of the defect is evaluated according to the center-of-gravity position. The uniformity is related to quality of a processed wafer.

Abstract: A method of manufacturing an epitaxy substrate is provided. A handle substrate is provided. A beveling treatment is performed on an edge of a device substrate such that a bevel is formed at the edge of the device substrate, wherein a thickness of the device substrate is greater than 100 ?m and less than 200 ?m. An ion implantation process is performed on a first surface of the device substrate to form an implantation region within the first surface. A second surface of the device substrate is bonded to the handle substrate for forming the epitaxy substrate, wherein a bonding angle greater than 90° is provided between the bevel of the device substrate and the handle substrate, and a projection length of the bevel toward the handle substrate is between 600 ?m and 800 ?m.

Abstract: A method for growing a single crystal silicon ingot by the continuous Czochralski method is disclosed. The melt depth and thermal conditions are constant during growth because the silicon melt is continuously replenished as it is consumed, and the crucible location is fixed. The critical v/G is determined by the hot zone configuration, and the continuous replenishment of silicon to the melt during growth enables growth of the ingot at a constant pull rate consistent with the critical v/G during growth of a substantial portion of the main body of the ingot. The continuous replenishment of silicon is accompanied by periodic or continuous nitrogen addition to the melt to result in a nitrogen doped ingot.

Abstract: A method for growing a single crystal silicon ingot by the continuous Czochralski method is disclosed. The melt depth and thermal conditions are constant during growth because the silicon melt is continuously replenished as it is consumed, and the crucible location is fixed. The critical v/G is determined by the hot zone configuration, and the continuous replenishment of silicon to the melt during growth enables growth of the ingot at a constant pull rate consistent with the critical v/G during growth of a substantial portion of the main body of the ingot. The continuous replenishment of silicon is accompanied by periodic or continuous nitrogen addition to the melt to result in a nitrogen doped ingot.

Abstract: A liner assembly for a substrate processing system includes a first liner and a second liner. The first liner includes an annular body and an outer peripheral surface including a first fluid guide. The first fluid guide is curved about a circumferential line extending around the first liner. The second liner includes an annular body, an outer rim, an inner rim, a second fluid guide extending between the outer rim and the inner rim, and a plurality of partition walls extending outwardly from the second fluid guide. The second fluid guide is curved about the circumferential line when the first and second liners are positioned within the processing system.

Abstract: A method for producing a silicon ingot includes withdrawing a seed crystal from a melt that includes melted silicon in a crucible that is enclosed in a vacuum chamber containing a cusped magnetic field. At least one process parameter is regulated in at least two stages, including a first stage corresponding to formation of the silicon ingot up to an intermediate ingot length, and a second stage corresponding to formation of the silicon ingot from the intermediate ingot length to the total ingot length. During the second stage process parameter regulation may include reducing a crystal rotation rate, reducing a crucible rotation rate, and/or increasing a magnetic field strength relative to the first stage.

Abstract: A method for producing Si ingot single crystal including a Si ingot single crystal growing step, a temperature gradient controlling step and a continuous growing step is provided. In the growing step, the Si ingot single crystal is grown in silicon melt in crucible, and the growing step includes providing a low-temperature region in the Si melt and providing a silicon seed to contact the melt surface of the silicon melt to start crystal growth, and silicon single crystal grows along the melt surface of the silicon melt and toward the inside of the silicon melt. In the temperature gradient controlling step, the under-surface temperature gradient of the silicon single crystal is G1, the above-surface temperature gradient of the silicon single crystal is G2, G1 and G2 satisfy: G2/G1<6. The step of controlling the temperature gradient of silicon single crystal is repeated to obtain the Si ingot single crystal.