Patents Assigned to GLOBALWAFERS CO., LTD.
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Patent number: 11845030Abstract: A dust collecting system for single crystal growth system includes an air compressor, a dust collecting device, a first inert gas source, a rotary pump and a scrubber. The air compressor is fluidly connected to an exit pipe of the single crystal growth system. The exit pipe is used to exhaust unstable dust from the single crystal growth system. The dust collecting device is fluidly connecting to the exit pipe to collect the dust oxide. The first inert gas source is fluidly connected to the exit pipe to blow a first inert gas into the exit pipe to compel the dust oxide toward the dust collecting device. The rotary pump is fluidly connected to the dust collecting device. The scrubber is fluidly connected to the rotary pump. The rotary pump transports the residual dust oxide toward the scrubber. The present disclosure further provides a method for collecting dust.Type: GrantFiled: June 22, 2020Date of Patent: December 19, 2023Assignee: GlobalWafers Co., Ltd.Inventors: Masami Nakanishi, Yu-Sheng Su, I-Ching Li
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Patent number: 11837632Abstract: Provided is a wafer including a ring part and a processed part. The processed part is connected to the ring part. The processed part has a top surface which has been grounded and a bottom surface opposite to the top surface. The processed part is surrounded by the ring part. A region where the top surface connects to the ring part is a curved surface curved upwards.Type: GrantFiled: January 24, 2022Date of Patent: December 5, 2023Assignee: GlobalWafers Co., Ltd.Inventors: Chan-Ju Wen, Chih-Wei Chang, Su Lien Chou
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Publication number: 20230378278Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and 0?y?1; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers. The aluminum content varies continuously throughout a thickness of at least one of the layers.Type: ApplicationFiled: July 14, 2023Publication date: November 23, 2023Applicant: GlobalWafers Co., Ltd.Inventors: Jia-Zhe Liu, Chih-Yuan Chuang, Po Jung Lin, Hong Che Lin
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Patent number: 11821105Abstract: The disclosure provides a silicon carbide seed crystal and a method of manufacturing a silicon carbide ingot. The silicon carbide seed crystal has a silicon surface and a carbon surface opposite to the silicon surface. A difference D between a basal plane dislocation density BPD1 of the silicon surface and a basal plane dislocation density BPD2 of the carbon surface satisfies the following formula (1), a local thickness variation (LTV) of the silicon carbide seed crystal is 2.5 ?m or less, and a stacking fault (SF) density of the silicon carbide seed crystal is 10 EA/cm2 or less: D=(BPD1?BPD2)/BPD1?25%??(1).Type: GrantFiled: July 27, 2021Date of Patent: November 21, 2023Assignee: GlobalWafers Co., Ltd.Inventor: Ching-Shan Lin
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Publication number: 20230369447Abstract: A method of manufacturing a high electron mobility transistor (HEMT) structure is disclosed. By controlling a passivation layer and a barrier layer to uninterruptedly grow in the same growth chamber, defects of the passivation layer generated in the growth process due to a drastic change in temperature, pressure, or atmosphere or degrading a quality of an interface between the passivation layer and the barrier layer could be avoided, thereby providing the passivation layer with a good quality and the interface between the passivation layer and the barrier layer with a good quality, so that the objective of improving the performance of the HEMT structure could be achieved.Type: ApplicationFiled: April 3, 2023Publication date: November 16, 2023Applicant: GLOBALWAFERS CO., LTD.Inventors: JIA-ZHE LIU, TZU-YAO LIN
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Publication number: 20230360909Abstract: A method of manufacturing an epitaxial structure includes steps of: A: provide a silicon carbide (SiC) substrate, wherein a silicon face (Si-face) of the SiC substrate is taken as a growth face having an off-angle relative to the Si-face of the SiC substrate; B: deposit a nitride angle adjustment layer having a thickness less than 50 nm on the growth face of the SiC substrate through physical vapor deposition (PVD); C: deposit a first group III nitride layer on the nitride angle adjustment layer; and D: deposit a second group III nitride layer on the first group III nitride layer. Through the method of manufacturing the epitaxial structure, when the silicon face of the silicon carbide substrate has the off-angle, the problem of a poor epitaxial quality of the first group III nitride layer and a poor epitaxial quality of the second group III nitride layer could be effectively relieved.Type: ApplicationFiled: February 1, 2023Publication date: November 9, 2023Applicant: GLOBALWAFERS CO., LTD.Inventors: PO-JUNG LIN, HAN-ZONG WU
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Publication number: 20230360910Abstract: A method of manufacturing an epitaxial structure includes steps of: A: provide a silicon carbide (SiC) substrate, wherein a silicon face (Si-face) of the SiC substrate is taken as a growth face, and the growth face has an off-angle relative to the Si-face of the SiC substrate; B: deposit a nitride angle adjustment layer on the growth face of the SiC substrate through physical vapor deposition (PVD); C: deposit a first group III nitride layer on the nitride angle adjustment layer; and D: deposit a second group III nitride layer on the first group III nitride layer. Through the method of manufacturing the epitaxial structure, when the silicon face of the silicon carbide substrate has the off-angle, the problem of a poor epitaxial quality of the first group III nitride layer and a poor epitaxial quality of the second group III nitride layer could be effectively relieved.Type: ApplicationFiled: February 1, 2023Publication date: November 9, 2023Applicant: GLOBALWAFERS CO., LTD.Inventors: PO-JUNG LIN, HAN-ZONG WU
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Publication number: 20230357916Abstract: A method of manufacturing an epitaxial structure includes steps of: A: provide a silicon nitride (SiC) substrate having a carbon face (C-face) without an off-angle; B: form an amorphous structure layer on the C-face of the SiC substrate; C: deposit a first group III nitride layer on the amorphous structure layer; and D: deposit a second group III nitride layer on the first group III nitride layer. By forming the amorphous structure layer, a top surface of the second group III nitride layer could be made to be in a flat and smooth state.Type: ApplicationFiled: February 1, 2023Publication date: November 9, 2023Applicant: GLOBALWAFERS CO., LTD.Inventors: PO-JUNG LIN, HAN-ZONG WU
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Publication number: 20230343588Abstract: A semiconductor structure includes a silicon carbide (SiC) substrate, a nucleation layer and a gallium nitride (GaN) layer. The silicon carbide layer has a first thickness T1. The nucleation layer is located on the silicon carbide layer and has a second thickness T2. The nucleation layer is made of AlGaN (AlGaN), and the second thickness T2 fulfills a thickness range of T1*0.002% to T1*0.006%. The gallium nitride layer is located on the nucleation layer and is separated from the silicon carbide substrate.Type: ApplicationFiled: April 10, 2023Publication date: October 26, 2023Applicant: GlobalWafers Co., Ltd.Inventors: Po Jung Lin, Jia-Zhe Liu
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Patent number: 11795571Abstract: Methods for growing a single crystal silicon ingot are disclosed. A dynamic state chart that monitors a plurality of ingot growth parameters may be produced and used during production of single crystal silicon ingots. In some embodiments, the dynamic state chart is a dynamic circle map chart having a plurality of sectors with each sector monitoring an ingot growth parameter.Type: GrantFiled: July 6, 2022Date of Patent: October 24, 2023Assignee: GlobalWafers Co., Ltd.Inventors: Giorgio Agostini, Stephan Haringer, Marco Zardoni
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Patent number: 11798802Abstract: Methods for removing an oxide film and for cleaning silicon-on-insulator structures are disclosed. The methods may involve immersing the silicon-on-insulator structure in a stripping bath to strip an oxide film from the surface of the silicon-on-insulator structure. The stripped silicon-on-insulator structure is immersed in an ozone bath comprising ozone. The ozone-treated silicon-on-insulator structure may be immersed in an SC-1 bath comprising ammonium hydroxide and hydrogen peroxide to clean the structure.Type: GrantFiled: February 11, 2022Date of Patent: October 24, 2023Assignee: GlobalWafers Co., Ltd.Inventors: Qingmin Liu, Haihe Liang, Junting Yang
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Patent number: 11795569Abstract: An ingot puller apparatus for producing a doped single crystal silicon ingot includes a housing defining a chamber, a crucible disposed within the chamber, and a dopant injector extending into the housing. The dopant injector includes a delivery module attached to and extending through the housing into the chamber. The delivery module includes a dopant injection tube positioned within the chamber and a vaporization cup positioned within the dopant injection tube and the chamber. The second valve selectively channels the liquid dopant into the vaporization cup and the vaporization cup vaporizes the liquid dopant into a vaporized dopant.Type: GrantFiled: December 31, 2020Date of Patent: October 24, 2023Assignee: GlobalWafers Co., Ltd.Inventors: Yu-Chiao Wu, William Lynn Luter, Richard J. Phillips, James Dean Eoff
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Patent number: 11798835Abstract: Methods for removing an oxide film from a silicon-on-insulator structure are disclosed. The oxide may be stripped from a SOI structure before deposition of an epitaxial silicon thickening layer. The oxide film may be removed by dispensing an etching solution toward a center region of the SOI structure and dispensing an etching solution to an edge region of the structure.Type: GrantFiled: February 8, 2022Date of Patent: October 24, 2023Assignee: GlobalWafers Co., Ltd.Inventors: Charles R. Lottes, Shawn George Thomas, Henry Frank Erk
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Patent number: 11788204Abstract: A silicon carbide wafer is provided, wherein within a range area of 5 mm from an edge of the silicon carbide wafer, there are no low angle grain boundaries formed by clustering of basal plane dislocation defects, and the silicon carbide wafer has a bowing of less than 15 ?m.Type: GrantFiled: July 27, 2021Date of Patent: October 17, 2023Assignee: GlobalWafers Co., Ltd.Inventor: Ching-Shan Lin
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Patent number: 11781241Abstract: A silicon carbide seed crystal and method of manufacturing the same, and method of manufacturing silicon carbide ingot are provided. The silicon carbide seed crystal has a silicon surface and a carbon surface opposite to the silicon surface. A difference D between a basal plane dislocation density BPD1 of the silicon surface BPD1 and a basal plane dislocation density BPD2 of the carbon surface satisfies the following formula (1): D=(BPD1?BPD2)/BPD1?25%??(1).Type: GrantFiled: July 27, 2021Date of Patent: October 10, 2023Assignee: GlobalWafers Co., Ltd.Inventor: Ching-Shan Lin
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Publication number: 20230304185Abstract: A method for producing Si ingot single crystal by NOC growth method including a Si ingot single crystal growing step and a continuous growing step is provided. The growing step includes providing a low temperature region in the Si melt where the Si ingot single crystal is grown along the surface of the Si melt or toward the inside of the Si melt, and the Si ingot single crystal has distribution of a vacancy concentration and an interstitial concentration in which respectively a vacancy concentration and an interstitial concentration vary with a distance from the growth interface; and adjusting a temperature gradient and a growth rate in the Si melt, so that along with the increasing of the distance from the growth interface, the vacancy concentration and the interstitial concentration in the Si ingot single crystal respectively decrease come near to each other.Type: ApplicationFiled: May 30, 2023Publication date: September 28, 2023Applicant: GlobalWafers Co., Ltd.Inventors: Kazuo Nakajima, Masami Nakanishi, Yu Sheng Su, Wen-Ching Hsu
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Patent number: 11767611Abstract: Methods for producing monocrystalline silicon ingots by horizontal magnetic field Czochralski are disclosed. During growth of the neck and/or growth of at least a portion of the crown, a magnetic field is not applied to the neck and/or crown or a relatively weak magnetic field of 1500 gauss or less is applied. A horizontal magnetic field (e.g., greater than 1500 gauss) is applied during growth of the ingot main body.Type: GrantFiled: May 25, 2021Date of Patent: September 26, 2023Assignee: GlobalWafers Co., Ltd.Inventors: JaeWoo Ryu, Carissima Marie Hudson, JunHwan Ji, WooJin Yoon
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Patent number: 11767610Abstract: Methods for producing single crystal silicon ingots by Continuous Czochralski (CCz) are disclosed. A batch of buffer members (e.g., quartz cullets) is added to an outer melt zone of the crucible assembly before the main body of the ingot is grown. In some embodiments, the ratio of the mass M of the batch of buffer members added to the melt to the time between adding the batch of buffer members to the melt and when the ingot main body begins to grow is controlled such that the ratio of M/T is greater than a threshold M/T.Type: GrantFiled: December 16, 2021Date of Patent: September 26, 2023Assignee: GlobalWafers Co., Ltd.Inventors: Matteo Pannocchia, Francesca Marchese, James Ho Wai Kitt
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Publication number: 20230295833Abstract: A method for producing Si ingot single crystal by NOC growth method including a Si ingot single crystal growing step and a continuous growing step is provided. The growing step includes providing a low temperature region in the Si melt where the Si ingot single crystal is grown along the surface of the Si melt or toward the inside of the Si melt, and the Si ingot single crystal has distribution of a vacancy concentration and an interstitial concentration in which respectively a vacancy concentration and an interstitial concentration vary with a distance from the growth interface; and adjusting a temperature gradient and a growth rate in the Si melt, so that along with the increasing of the distance from the growth interface, the vacancy concentration and the interstitial concentration in the Si ingot single crystal respectively decrease come near to each other.Type: ApplicationFiled: May 30, 2023Publication date: September 21, 2023Applicant: GlobalWafers Co., Ltd.Inventors: Kazuo Nakajima, Masami Nakanishi, Yu Sheng Su, Wen-Ching Hsu
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Patent number: 11764071Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.Type: GrantFiled: June 11, 2019Date of Patent: September 19, 2023Assignee: GlobalWafers Co., Ltd.Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht