Patents Assigned to Inpaq Technology Co., Ltd.
  • Publication number: 20110204521
    Abstract: A chip-scale semiconductor device package includes a die, an insulating substrate having a through hole, a first metal layer, a second metal layer, and an insulating layer. The first metal layer is on a first surface of the insulating substrate and a first side of the through hole. The insulating layer is overlaid on a second surface of the insulating substrate and surrounds a second side of the through hole. The second metal is on the insulating layer and the second side of the through hole. The die is in the through hole and includes a first electrode and a second electrode. The first electrode is electrically connected to the first metal layer, and the second electrode is electrically connected to the second metal layer.
    Type: Application
    Filed: February 18, 2011
    Publication date: August 25, 2011
    Applicant: INPAQ TECHNOLOGY CO., LTD.
    Inventors: LIANG CHIEH WU, CHENG YI WANG
  • Patent number: 7884462
    Abstract: An insulation covering structure for a semiconductor element with a single die dimension includes: a semiconductor element with a single die dimension and an insulation covering layer. The semiconductor element has a front side surface, a rear side surface, a left side surface, a right side surface, a bottom surface, and a top surface. The top surface of the semiconductor element has two metal pads. The insulation covering layer covers the front side surface, the rear side surface, the left side surface, the right side surface, and the bottom surface of the semiconductor element. A manufacturing process for covering the semiconductor element with a single die dimension is also disclosed.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: February 8, 2011
    Assignee: Inpaq Technology Co., Ltd.
    Inventors: Liang-Chieh Wu, Hui-Ming Feng
  • Publication number: 20110025442
    Abstract: A common mode filter comprises an insulating substrate, a lower coil leading layer, a coil main body multilayer, and an upper coil leading layer. The upper coil leading layer comprises at least one upper lead, at least one upper terminal, and at least one upper contact, and the lower coil leading layer comprises at least one lower lead, at least one lower terminal, and at least one lower contact. The two ends of the upper lead are respectively connected to the upper terminal and the upper contact, and the upper lead surrounds the upper contact. The two ends of the lower lead are respectively connected to the lower terminal and the lower contact, and the lower lead surrounds the lower contact. The upper coil leading layer and the lower coil leading layer sandwich the coil main body multi-layer, and the lower coil leading layer is disposed on the insulating substrate.
    Type: Application
    Filed: March 18, 2010
    Publication date: February 3, 2011
    Applicant: INPAQ TECHNOLOGY CO., LTD.
    Inventors: MING LIANG HSIEH, MING YI YANG, LIANG CHIEH WU, SHENG FU SU, CHENG YI WANG
  • Publication number: 20100309087
    Abstract: A chip antenna device includes a single or multi-layer dielectric substrate, a radiator body, one or a plurality of first coupling electrodes formed on the radiator body, and a ground radiator formed on the upper or lower surface or inter-layer in another end of the substrate. It is designed by using loops and coupling concepts. The chip antenna device does not require large areas and clear space but has high radiation efficiency. It adjusts the impedance matching and operation frequency by changing the signal feed position, so that low frequency operation can be achieved without increasing the area of said antenna meeting the requirements of compact size for electronic products.
    Type: Application
    Filed: June 4, 2009
    Publication date: December 9, 2010
    Applicant: INPAQ TECHNOLOGY CO., LTD.
    Inventors: Yueh-Lin Tsai, Sheng-Kai Wen, Chih-Wei Chen
  • Patent number: 7821368
    Abstract: A thin film type common mode noise filter and its fabrication method are disclosed. There are several electric insulation layers, coil lead layers and main coil layers are formed on an insulation substrate by means of processes of Lithography, Physical Vapor Deposition, etching or other chemical process. After that the structure is covered with an electric insulation gluing layer and a magnetic material layer so as to form a thin film type common mode noise filter with a low production cost but an improved filtering characteristic of the common mode noise.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: October 26, 2010
    Assignee: Inpaq Technology Co., Ltd.
    Inventors: Ming Yi Yang, Zheng Yi Wang, Ming Liang Hsieh, Sheng Fu Su
  • Patent number: 7800550
    Abstract: A dipole antenna array includes a dielectric substrate; electric tuning elements mounted on a first surface and a second surface of the dielectric substrate; resonance elements and ground elements; and a feed line. Each resonance element includes first resonance parts, second resonance parts and a third resonance part. One of the second resonance parts connects the corresponding first resonance part to the third resonance part. The other second resonance parts respectively connect two neighboring first resonance parts. Each ground element includes first ground parts, second ground parts and a third ground part. One of the second ground parts connects one of the first ground parts to the third ground part. The other second ground parts respectively connect to two neighboring first ground parts.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: September 21, 2010
    Assignee: Inpaq Technology Co., Ltd.
    Inventors: Lee-Ting Hsieh, Chih-Hao Lai
  • Publication number: 20100182121
    Abstract: An over-current protection device comprises a PTC material layer, a first electrode layer, a second electrode layer, a first side electrode and a second side electrode. The PTC material layer is sandwiched between the first electrode layer and the second electrode layer. The first side electrode and the second side electrode are respectively disposed on two opposite side surfaces of the PTC material layer, and are respectively connected to the first electrode layer and the second electrode layer. Furthermore, the first side electrode and the second side electrode are respectively extended to four surfaces adjacent and perpendicular to the two side surfaces.
    Type: Application
    Filed: May 20, 2009
    Publication date: July 22, 2010
    Applicant: INPAQ TECHNOLOGY CO., LTD.
    Inventors: WEN CHIN LI, HUI MING FENG
  • Publication number: 20100164809
    Abstract: A circular polarization antenna structure with a dual-layer ceramic includes a first hard dielectric body, a first metal layer, a grounding layer, an antenna feed pin, a second hard dielectric body, a second metal layer and an adhesive element. The first metal layer and the grounding layer dispose on a top surface and a bottom surface of the first hard dielectric body. The antenna feed pin passes through the through hole of the first hard dielectric body, the top side of the antenna feed pin is fixed on the top surface of the first hard dielectric body, and the bottom side of the antenna feed pin extends outwards from the bottom surface of the first hard dielectric body. The second hard dielectric body disposes above the top side of the first hard dielectric body. The second metal layer disposes on the top surface of the second hard dielectric body.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Applicant: INPAQ TECHNOLOGY CO., LTD.
    Inventors: TA-FU CHENG, HUI-CHIEH WANG, YUAN-PIAO TSENG
  • Patent number: 7741948
    Abstract: A laminated variable resistor comprises a main body, internal electrodes extending along two side edges of the main body into the main body, terminal electrodes disposed on the two ends of the main body. The mole percentage of the oxide in overlapping active regions between opposite internal electrodes is reduced and the reduced portion is replaced by a metal selected from gold (Au), silver (Ag), palladium (Pd), platinum (Pt), rhodium (Rh), or the alloy of any two of such metals.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: June 22, 2010
    Assignee: Inpaq Technology Co., Ltd.
    Inventors: Shih-Kwan Liu, Hui-Ming Feng
  • Patent number: 7741709
    Abstract: An embedded type multifunctional integrated structure for integrating protection components and a method for manufacturing the same are disclosed. The present invention utilizes the concept of multi-layer design to integrate more than two passive components on a component structure that is adhered onto a substrate and is applied to a USB terminal in order to protect an electronic device that uses the USB. Hence, the present invention has an OCP function, an OVP function, and an anti-ESD function at the same time. Therefore, the present invention effectively integrates two or more passive components in order to increase functionality. Moreover, the present invention effectively reduces the size of the passive components on a PCB and reduces the number of solder joints.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: June 22, 2010
    Assignee: Inpaq Technology Co., Ltd.
    Inventors: Chien-Hao Huang, Wen-Chih Li
  • Patent number: 7714785
    Abstract: A GPS (Global Positioning System) antenna module includes a substrate, a first insulating layer, and a second insulating layer. The substrate is set on a bottom surface of a patch antenna. The first insulating layer is coated on the substrate and a layout circuit is formed thereon. A plurality of electronic elements are integrated on the substrate according to the layout circuit. Furthermore, the second insulating layer is coated on the first insulating layer to completely shield the electronic elements integrated on the substrate. Hence, the distance between the electronic elements and the antenna of the present invention can be shortened, space on the PCB and in the shielding case is saved. Moreover, an optimal high frequency character can be achieved, the volume of the antenna module is effectively reduced, the process is simplified, and production costs are reduced.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: May 11, 2010
    Assignee: Inpaq Technology Co., Ltd.
    Inventors: Kang-Neng Hsu, Yueh-Lin Tsai, Chih-Hsin Chiu, Jyun-Ren Wang
  • Patent number: 7715164
    Abstract: An embedded type multifunctional integrated structure and a method for manufacturing the same are disclosed. The present invention utilizes the concept of multi-layer design to integrated more than two passive components on a component structure that would be adhered to a substrate. Hence, the embedded type multifunctional integrated structure has an OCP function, an OVP function, an anti-EMI function, and an anti-ESD function at the same time. Therefore, the present invention effectively integrated two or more than one passive components in order to increase function of the embedded type multifunctional integrated structure. Moreover, the present invention effectively reduces the size of the passive components on a PCB and reduces the number of solder joints.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: May 11, 2010
    Assignee: Inpaq Technology Co., Ltd.
    Inventors: Chien-Hao Huang, Wen-Chih Li
  • Publication number: 20100078798
    Abstract: An insulation covering structure for a semiconductor element with a single die dimension includes: a semiconductor element with a single die dimension and an insulation covering layer. The semiconductor element has a front side surface, a rear side surface, a left side surface, a right side surface, a bottom surface, and a top surface. The top surface of the semiconductor element has two metal pads. The insulation covering layer covers the front side surface, the rear side surface, the left side surface, the right side surface, and the bottom surface of the semiconductor element. A manufacturing process for covering the semiconductor element with a single die dimension is also disclosed.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Applicant: INPAQ TECHNOLOGY CO., LTD.
    Inventors: Liang-Chieh Wu, Hui-Ming Feng
  • Publication number: 20090296294
    Abstract: The present invention relates to an electro-static discharge (ESD) protection device with a low temperature co-fire ceramic (LTCC) and a manufacturing method thereof. The ESD protection device comprises a low temperature co-fire ceramic film having a first patterned conductive electrode material layer and a second patterned conductive electrode material layer therein. The low temperature co-fire ceramic film has at least one via exposing a portion of the first patterned conductive electrode material layer and a portion of the second patterned conductive electrode material layer simultaneously.
    Type: Application
    Filed: February 23, 2009
    Publication date: December 3, 2009
    Applicant: INPAQ TECHNOLOGY CO., LTD.
    Inventor: Te-Pang Liu
  • Patent number: 7609143
    Abstract: A multi-layer type over-current and over-temperature protection structure and a method of manufacturing the same are disclosed. The present invention utilizes the concept of multi-layer design to integrate more than two over-current and over-temperature protection elements on a component structure that can be adhered to a substrate. Hence, the over-current and over-temperature protection structure has more than two over-current and over-temperature protection functions at the same time. Therefore, the advantages of the present invention is that the over-current and over-temperature protection structure effectively integrates two or more over-current and over-temperature protection elements together in order to increase the usage range of the over-current and over-temperature protection structure. Moreover, the present invention effectively reduces size of the over-current and over-temperature protection elements on a PCB and reduces the number of solder joints.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: October 27, 2009
    Assignee: Inpaq Technology Co., Ltd.
    Inventor: Chien-Hao Huang
  • Patent number: 7592203
    Abstract: A method of manufacturing an electronic protection device comprises: providing a substrate mother board with a top surface and a bottom surface; forming a first conductive layer and a second conductive layer on the top surface and the bottom surface, respectively; cutting the substrate mother board into a plurality of strip-shaped substrates; and forming insulating layers on surfaces of each of the strip-shaped substrates that are not covered by the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: September 22, 2009
    Assignee: Inpaq Technology Co., Ltd.
    Inventors: Chien-Hao Huang, Wen-Chih Li
  • Patent number: 7576697
    Abstract: A dual polarization antenna device for creating a dual band function, includes: a first dielectric body, a patch layer, a first phase difference changing structure, a second dielectric body, a common metal layer, a ground layer, a second phase difference changing structure, a first antenna feed pin, and a second antenna feed pin. The first dielectric body, the patch layer, the first phase difference changing structure, the common metal layer, and the first antenna feed pin are combined together to form an upper polarization antenna structure. The second dielectric body, the common metal layer, the second phase difference changing structure, and the ground layer are combined together to form a lower polarization antenna structure. Therefore, the upper polarization antenna structure and the lower polarization antenna structure are combined to create both the dual polarization and the dual band functions.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: August 18, 2009
    Assignee: Inpaq Technology Co., Ltd.
    Inventors: Chih-Ming Chen, Min-Sheng Ma, Yuch-Pi Huang
  • Patent number: 7554509
    Abstract: A column antenna apparatus and a manufacturing method thereof are disclosed. This invention forms a metal layer with at least two spiral structures on a column body. The column antenna apparatus can simplify the manufacturing process and enhance the yield rate. The column antenna apparatus includes a column body, a metal layer and at least two spiral structures. The metal layer is formed on the surface of the column body, and the at least two spiral structures are formed on the metal layer for increasing bandwidth of low frequency. Each spiral structure is formed by removing a part of the metal layer, and the column body is exposed via the at least two spiral structures.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: June 30, 2009
    Assignee: Inpaq Technology Co., Ltd.
    Inventors: Kang-Neng Hsu, Chih-Ming Chen, Liang-Neng Lee, Kuo-Wei Wu
  • Publication number: 20090128281
    Abstract: A composite chip varistor device includes a body; at least one inner varistor, disposed in the body; and a plurality of end electrodes, disposed at two sides of the inner varistor. The body is a highly insulative and imporous mono-material. The body of the present invention provides protection for the inner varistor to avoid being damaged by external factors and the manufacturing cost of the varistor device is effectively reduced.
    Type: Application
    Filed: February 22, 2008
    Publication date: May 21, 2009
    Applicant: INPAQ TECHNOLOGY CO., LTD.
    Inventor: YUNG-CHI CHEN
  • Patent number: 7528467
    Abstract: The present invention relates to an IC substrate provided with over voltage protection functions and thus, a plurality of over voltage protection devices are provided on a single substrate to protect an IC chip directly. According to the present invention, there is no need to install protection devices at respective I/O ports on a printed circuit board to prevent the IC devices from damage by surge pulses. Therefore, the costs to design circuits are reduced, the limited space is efficiently utilized, and unit costs to install respective protection devices are lowered down.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: May 5, 2009
    Assignee: Inpaq Technology Co., Ltd.
    Inventor: Chun-Yuan Lee