Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) for software defined silicon guardianship are disclosed.

Abstract: This disclosure relates matrix operation acceleration for different matrix sparsity patterns. A matrix operation accelerator may be designed to perform matrix operations more efficiently for a first matrix sparsity pattern rather than for a second matrix sparsity pattern. A matrix with the second sparsity pattern may be converted to a matrix with the first sparsity pattern and provided to the matrix operation accelerator. By rearranging the rows and/or columns of the matrix, the sparsity pattern of the matrix may be converted to a sparsity pattern that is suitable for computation with the matrix operation accelerator.

Abstract: Digital holographic microscopy and related image processing techniques are described. A hologram captured in an image frame is split into different depths while a new hologram is being captured. Image slices of the hologram are determined and using free space impulse responses that are pre-calculated at a different precision than processing operations using the holographic data. Each computation is calculated in parallel based on the number of available processing cores and threads. The image slices are combined into a 2D array or 3D array to permit further processing of the combined array to count and size particles in the image frame. The reconstructed hologram is displayed at a subsequent image frame than that used to capture the hologram.

Abstract: A method and system of image processing of omnidirectional images with a viewpoint shift.

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

Abstract: A long-term object tracker employs a continuous learning framework to overcome drift in the tracking position of a tracked object. The continuous learning framework consists of a continuous learning module that accumulates samples of the tracked object to improve the accuracy of object tracking over extended periods of time. The continuous learning module can include a sample pre-processor to refine a location of a candidate object found during object tracking, and a cropper to crop a portion of a frame containing a tracked object as a sample and to insert the sample into a continuous learning database to support future tracking.

Abstract: Systems and techniques for information centric network (ICN) interworking are described herein. For example, a request may be received at a convergence layer of a node. Here, the request originates from an application on the node. A network protocol, from several available to the node, may be determined to transmit the request. The node then transmits the request via the selected network protocol.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch, a bridge substrate over the glass substrate, a first die electrically coupled to first pads and the bridge substrate, and a second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die.

Abstract: Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.

Abstract: Disclosed herein are methods for manufacturing IC components using bottom-up fill of openings with a dielectric material. In one aspect, an exemplary method includes, first, depositing a solid dielectric liner on the inner surfaces of the openings using a non-flowable process, and subsequently filling the remaining empty volume of the openings with a fill dielectric using a flowable process. Such a combination method may maximize the individual strengths of the non-flowable and flowable processes due to the synergetic effect achieved by their combined use, while reducing their respective drawbacks. Assemblies and devices manufactured using such methods are disclosed as well.

Abstract: An apparatus includes a non-planar semiconductor body; and a contact for the semiconductor body. The contact includes an epitaxial material that is formed on and contacts the semiconductor body. The contact includes a second material that is formed on and contacts the epitaxial material; and the second material at least partially conforms to an undercut of the epitaxial material.

Abstract: An integrated circuit may include integrated memory that is formed from a chain of memory blocks. Each memory block may have configurable input and output circuits. The configurable input and output circuits may be interposed between memory circuitry such as a memory array from circuitry external to the memory circuitry. The configurable input and output circuits may have upstream and downstream memory block connection ports. In such a way, configurable input and output circuits in a first memory block may pass control and address signals and data to configurable input and output circuits in a second memory block. By using the configurable input and output circuits, the integrated memory in the integrated circuit may operate to accommodate large bandwidth flows without using the general routing fabric of the integrated circuit.

Abstract: A disclosed example includes a plurality of display pixels; timing controller circuitry; driver circuitry on a same integrated circuit as the timing controller circuitry, the driver circuitry to drive the display pixels; and de-multiplexer circuitry to de-multiplex pixel data to send to the plurality of display pixels.

Abstract: Disclosed embodiments are related to distinguishing between listen-before talk (LBT) failure and LBT success, reducing the effect of invalid out-of-sync (OOS) indications and preventing false declaration of radio link failures (RLFs). Other embodiments may be described and/or claimed.

Abstract: Embodiments are directed to immutable watermarking for authenticating and verifying artificial intelligence (AI)-generated output. An embodiment of a system includes a processor of a monitoring system, wherein the processor is to: receive first content from an edge device and second content from an adversary system, wherein the first content comprises output of a machine learning (ML) model as applied to captured content at the edge device; receive a digital signature corresponding to the first content; process the digital signature to extract a global unique identifier (GUID) of the ML model that generated the first content; verify the extracted GUID against data obtained from a shared registry; in response to successfully verifying the extracted GUID, provide the first content for consumption at a monitoring consumption application; and in response to determining that the second content is not associated with a verifiable GUID, refuse the second content at the monitoring consumption application.

Abstract: A method, system, and computer program product, the method comprising: obtaining a data path representing flow of data in processing a service request within a network computing environment having system resources; analyzing the data path to identify usage of the system resources required by the service request processing; determining, based on the usage of the system resources, an optimization action expected to improve the usage of the system resources; and implementing the optimization action in accordance with the data path, thereby modifying operation of the cloud computing environment in handling future service requests.

Abstract: Various embodiments herein include techniques to indicate a reference subcarrier spacing (SCS) in a soft resource availability configuration for an integrated access and backhaul (IAB) distributed unit (DU)/mobile terminal (MT). For example, the reference SCS may be included in soft resource availability radio resource control (RRC) configuration AvailabilityCombinationsPerCell. Additionally, embodiments include mechanisms for dynamic soft availability indication with paired spectrum operation (e.g., frequency division duplex (FDD) operation). Other embodiments may be described and claimed.

Abstract: Methods, systems, and storage media are described for new radio downlink positioning reference signal (NR DL PRS) resource allocation and configuration. In particular, some embodiments relate to some embodiments relate to NR DL PRS resource configurations such as comb size, number of symbols, DL PRS resource time configuration (e.g., initial start time and periodicity), and providing formulas for calculation of seed for DL PRS sequence generation. Other embodiments may be described and/or claimed.