Abstract: An apparatus to facilitate inferred object shading is disclosed. The apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3D) geometry, latent space and representation of the one or more objects.

Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

Abstract: Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed in the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.

Abstract: Systems and methods of re-configuring PCI values for a NR cell and performing mobility robustness optimization are described. To reconfigure the PCI values. The NRM data and the PCI of candidate cells measurements are analyzed to detect a potential PCI collision or PCI confusion among NR cells. In response to detection of the potential PCI collision or confusion, a new PCI value for at least one NR cell is determined and instructions to re-configure the at least one NR cell with the new PCI value are sent to a producer of provisioning MnS. For MRO, a NF provisioning MnS with modifyMOIAttributes operation to configure MRO targets for an MRO function and to enable the MRO function for a NR cell are consumed, as is a performance assurance MnS with a notifyFileReady or reportStreamData operation to collect MRO-related performance measurements. The measurements are analyzed to evaluate MRO performance.

Abstract: Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

Abstract: For example, an apparatus may be configured to generate, transmit, receive and/or process a frame including a multiple Basic Service Set Identifier (BSSID) element corresponding to a multiple BSSID set including a reporting AP, the BSSID element including one or more non-transmitted BSSID profile elements corresponding to one or more other APs belonging to the multiple BSSID set, wherein a non-transmitted BSSID profile element corresponding to an other AP includes one or more elements of information corresponding to the other AP, and a multi-link element, the multi-link element including one or more profile subelements for one or more reported APs of an other MLD including the other AP, respectively, wherein a profile subelement corresponding to a reported AP includes one or more elements of information corresponding to the reported AP.

Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

Abstract: Deep learning models, such as diffusion models, can synthesize images from noise. Diffusion models implement a complex denoising process involving many denoising operations. It can be a challenge to understand the mechanics of diffusion models. To better understand how and when structure is formed, saliency maps and concept formation intensity can be extracted from the sampling network of a diffusion model. Using the input map and the output map of a given denoising operation in a sampling network, a noise gradient map representative of the predicted noise of a given denoising operation can be determined. The noise gradient maps from the denoising operations at different indices can be combined to generate a saliency map. A concept formation intensity value can be determined from a noise gradient map. Concept formation intensity values from the denoising operations at different indices can be plotted.

Abstract: This disclosure describes systems, methods, and devices related to coexistence network integration. A device may transmit a beacon frame or a probe response frame containing a security element that is not a robust security network element (RSNE) element to indicate opportunistic wireless encryption (OWE) support. The device may identify a first association request frame received from a first station device (STA) comprising an RSNE element with OWE Authentication Key Management (AKM) indicating a compatibility of the first STA with OWE. The device may identify a second association request frame from a second station device (STA) indicating no compatibility with OWE. The device may generate one or more encryption keys for securing data transmission with OWE-compatible STAs. The device may transmit encrypted and unencrypted versions of groupcast data frames to the first STA and the second STA.

Abstract: An apparatus comprising a memory device, a system on chip (SoC), including a central processing unit (CPU) to execute a virtual machine to retrieve data from the memory device and transmit the data to a remote input/output (I/O) device coupled to a remote computing platform as memory transaction data; and a port to transmit the memory transaction data as transaction layer packets (TLPs) and a network interface card (NIC) to receive the TLPs, including an interface to receive the TLPs and packet conversion hardware to convert the TLPs to network protocol packets and transmit the network protocol packets to the remote I/O memory device.

Abstract: Embodiments are directed to protection of communications between a trusted execution environment and a hardware accelerator utilizing enhanced end-to-end encryption and inter-context security. An embodiment of an apparatus includes one or more processors having one or more trusted execution environments (TEEs) including a first TEE to include a first trusted application; an interface with a hardware accelerator, the hardware accelerator including trusted embedded software or firmware; and a computer memory to store an untrusted kernel mode driver for the hardware accelerator, the one or more processors to establish an encrypted tunnel between the first trusted application in the first TEE and the trusted software or firmware, generate a call for a first command from the first trusted application, generate an integrity tag for the first command, and transfer command parameters for the first command and the integrity tag to the kernel mode driver to generate the first command.

Abstract: An apparatus for clock manager redundancy comprises a clock circuitry to manage a clock for a device; a first processing circuitry coupled to the clock circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network; a hardened execution environment coupled to the clock circuitry and the first processing circuitry, the hardened execution environment to comprise: a detector to monitor the clock manager and generate an alert when the detector identifies abnormal behavior of the clock manager; and a second processing circuitry to execute instructions to perform operations for a redundant clock manager, the redundant clock manager to take over operations for the clock manager in response to the alert from the detector. Other embodiments are described and claimed.

Abstract: Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.

Abstract: Described herein is a technique to implement an efficient floating-point n-input sum of squares operation using faithful rounding to 1 unit in the place (ULP) instead of IEEE rounding. The resulting circuitry is useful to accelerate graphics algorithms that don't require fully IEEE compliant hardware. Multipliers that are 1ulp can be significantly smaller, faster and more power efficient than IEEE rounded multipliers.

Abstract: An integrated circuit structure includes a device layer including a first set of devices and a second set of devices. An interconnect layer is above the device layer, where the interconnect layer includes one or more conductive interconnect features within dielectric material. In an example, a first ring structure including conductive material extends within the interconnect layer, and a second ring structure including conductive material extends within the interconnect layer. In an example, the second ring structure is non-overlapping with the first ring structure. In an example, the first ring structure is above the first set of devices of the device layer, and the second ring structure is above the second set of devices of the device layer.

Abstract: Apparatus and method for non-local means filtering using a media processing block of a graphics processor. For example, one embodiment of a processor comprises: ray tracing circuitry to execute a first set of one or more commands to traverse rays through a bounding volume hierarchy (BVH) to identify BVH nodes and/or primitives intersected by the ray; shader execution circuitry to execute one or more shaders responsive to a second set of one or more commands to render a sequence of image frames based on the BVH nodes and/or primitives intersected by the ray; and a media processor comprising motion estimation circuitry to execute a third set of one or more commands to perform non-local means filtering to remove noise from the sequence of image frames based on a mean pixel value collected across the sequence of image frames.

Abstract: Magnetoelectric magnetic tunnel junction (MEMTJ) logic devices comprise a magnetoelectric switching capacitor coupled to a pair of magnetic tunnel junctions (MTJs) by a conductive layer. The logic state of the MEMTJ is represented by the magnetization orientation of the ferromagnetic layer of the magnetoelectric capacitor, which can be switched through the application of an appropriate input voltage to the MEMTJ. The magnetization orientation of the magnetoelectric capacitor ferromagnetic layer is read out by the MTJs. The conductive layer is positioned between the capacitor and the MTJs. The MTJ ferromagnetic free layers are exchange coupled to the ferromagnetic layer of the magnetoelectric capacitor. The potential of an MTJ free layer is based on a supply voltage applied to the reference layer of the MTJ. The MTJ reference layers have a magnetization orientation that is parallel or antiparallel to the magnetization orientations of the ferromagnetic layer of the magnetoelectric capacitor.

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

Abstract: An apparatus and method for conditional quality of service in a processor. For example, one embodiment of a processor comprises: a plurality of processor resources to be allocated to a plurality of executed processes in accordance with a set of quality of service (QoS) rules; and conditional quality of service (QoS) circuitry/logic to monitor usage of the plurality of processor resources by the plurality of processes and to responsively modify an allocation of a first processor resource for a first process in response to detecting a first threshold value being reached in a second resource allocated to the first process.

Abstract: Embodiments are generally directed to a flexible overlapping display. An embodiment of a mobile device includes a processor to process data for the mobile device, a bendable and foldable display screen, one or more device sensors to sense an orientation of the mobile device, and one or more display sensors to sense a current arrangement of the display screen. The processor is to identify one or more portions of the display screen that are visible to a user based at least in part on data from the one or more device sensors and the one or more display sensors.