Abstract: An apparatus including a proportional gain circuit, an integral gain circuit, a limit circuit, a gain booster circuit and a combiner. The gain circuits apply a proportional gain and an integral gain to an error signal, and the combiner combines both gained error signals to provide a control signal. The limit circuit applies a limit function that limits the proportional gain to a magnitude. The gain booster circuit increases gain while the limit function is being applied. The increased gain may be applied to only the integral gain, or to both the integral and proportional gains such as by boosting gain of the error signal. The apparatus may be a regulator that may include multiple control loops providing multiple error signals, in which a mode selector selects one of the error signals to control regulation. The limit function increases stability while the boosted gain improves transient response during mode transitions.

Abstract: A voltage error signal is provided to a PWM controller of a voltage regular and used to produce a PWM signal that drives a power stage of the regulator. When operating in an adapter current limit regulation mode, an adapter current sense voltage, indicative of an adapter current, is compared to an adapter current reference voltage to produce an adapter current error signal. A compensator receives the adapter current error signal and outputs a compensated adapter current error signal. The adapter current sense voltage, or a high pass filtered version thereof, is subtracted from the compensated adapter current error signal to produce the voltage error signal provided to the PWM controller. Alternatively, an input voltage, or a high pass filtered version thereof, is added to the compensated adapter current error signal to produce the voltage error signal.

Abstract: One embodiment is directed towards an encapsulated device. The encapsulated device includes a device, and a first encapsulation covering the device. The first encapsulation has one or more exterior surfaces. One or more recesses in one or more of the exterior surfaces is configured to receive a second encapsulation.

Abstract: The present embodiments relate to methods and apparatuses for providing fault protection in a power controller such as a voltage regulator, and particularly protection against reverse over current fault conditions. Some embodiments are capable of distinguishing between different types of reverse over current conditions, such as a high-side short or a normal over voltage condition. In these and other embodiments, fault protection is performed in favor of a load connected to the voltage regulator, rather than components of the voltage regulator itself.

Abstract: An electronic system, a multiple charger configuration, and method of operating a multiple input, multiple charger configuration are disclosed. For example, a multiple charger configuration is disclosed, which includes a first battery charger circuit configured to receive to a first input voltage, and a second battery charger circuit configured to receive a second input voltage. A first switching transistor is coupled to an output of the first battery charger circuit, a system voltage output terminal, and a battery terminal configured to connect to a battery stack or at least one battery cell. A second switching transistor is coupled to an output of the second battery charger circuit and the battery terminal. Thus, the multiple chargers can be utilized in one system to charge or discharge a battery stack or at least one battery cell and thereby deliver power for a battery-operated system, product or device.

Abstract: An embodiment of a power-supply controller includes first and second circuits. The first circuit is operable to cause a first current to flow through a first phase of a power supply. And the second circuit is operable to cause the second phase of the power supply to operate in a reduced-power-dissipation mode for at least a portion of a time period during which a second current magnetically induced by the first current flows through the second phase.

Abstract: A system, DC-DC converter, and compensation method and circuit for a DC-DC converter are disclosed. For example, a compensation circuit for a DC-DC converter is disclosed. The compensation circuit includes an integrator circuit configured to receive and integrate a first voltage signal, a differential difference amplifier circuit coupled to the integrator circuit and configured to generate a first filter transfer function associated with the integrated first voltage signal, and a switched capacitor filter circuit coupled to the differential difference amplifier circuit and configured to generate a second filter transfer function, wherein the differential difference amplifier is further configured to output a second voltage signal responsive to the first filter transfer function and the second filter transfer function. In one implementation, the compensation circuit is a type-III switched capacitor filter (SCF) compensation circuit.

Abstract: In an embodiment, a power supply includes first and second supply input nodes, a supply output node, first and second switch circuits, a filter circuit, and a drive circuit. The first and second supply input nodes are respectively configured to receive first and second input voltages, and the supply output node is configured to provide an output voltage. The first switch circuit has a first conduction node coupled to the first supply input node, a second conduction node, and a control node configured to receive a first control signal, and the filter circuit has a first node coupled to the second conduction node and has a second node. The second switch circuit has a first conduction node coupled to the second node of the filter circuit, a second conduction node coupled to the second supply input node, and a control node.

Abstract: A hysteretic current mode buck-boost voltage regulator including a buck-boost voltage converter, a switching controller, a window circuit, a ramp circuit, and a timing circuit. The timing circuit may be additional ramp circuits. The voltage converter is toggled between first and second switching states during a boost mode, is toggled between third and fourth switching states during a buck mode, and is sequentially cycled through each switching state during a buck-boost mode. The ramp circuit develops a ramp voltage that simulates current through the voltage converter, and switching is determined using the ramp voltage compared with window voltages provided by the window circuit. The window voltages establish frequency, and may be adjusted based on the input and output voltages. The timing circuit provides timing indications during the buck-boost mode to ensure that the second and fourth switching states have approximately the same duration to provide symmetry of the ramp signal.

Abstract: An optical proximity detector includes a driver, light detector, analog front-end and digital back end. The driver drives the light source to emit light. The light detector produces a light detection signal indicative of a magnitude and a phase of a portion of the emitted light that reflects off an object and is incident on the light detector. The analog front-end includes amplification circuitry, and one or more analog-to-digital converters (ADCs) that output a digital light detection signal, or digital in-phase and quadrature-phase signals indicative thereof. The digital back-end includes a distance calculator and a precision estimator. The distance calculator produces a digital distance value in dependence on the digital light detection signal, or the digital in-phase and quadrature-phase signals, output by the ADC(s) of the analog front-end. The precision estimator produces a precision value indicative of a precision of the digital distance value.

Abstract: A battery charge system including an adapter node, a system node, a battery, a first isolation switch coupled between the adapter and system nodes, a second isolation switch coupled between the battery and system nodes, a boost converter, and a controller. The controller turns off the first isolation switch and turns on the second isolation switch during a battery mode, activates the boost converter when an adapter voltage is detected, turns off the second isolation switch when the system voltage rises above the battery voltage, and turns on the first isolation switch when the system voltage rises to an operating voltage level. The boost converter may then be turned off once in the adapter mode. The second isolation switch may initially be turned on partially at a low current level when the adapter is detected, and then turned fully on when the system voltage is at the operating voltage level.

Abstract: Systems and methods for an open wire scan are provided. In certain embodiments, An apparatus comprising a circuit includes a plurality of inputs for connecting with a plurality of outputs of a multi-cell battery pack; and an open connection detection circuit, formed within the circuit, for detecting an open connection on at least one of the plurality of inputs connected to the multi-cell battery pack and generating a fault condition responsive thereto. The open connection detection circuit comprises at least one current source device; and at least one device for turning on and off the at least one current source device. The open connection detection circuit also comprises at least one amplifier; an analog to digital converter; and a control logic circuit.

Abstract: One embodiment pertains to a method including determining the duty cycle of a PWM signal, operating in valley current control mode when the duty cycle is greater than fifty percent, operating in peak current control mode when the duty cycle is less than fifty percent, and including, commencing a PWM pulse upon the occurrence of a pulse of a first clock signal pulse, and terminating the PWM pulse upon a level of a signal exceeding a positive window threshold.

Abstract: An apparatus including a proportional gain circuit, an integral gain circuit, a limit circuit, a gain booster circuit and a combiner. The gain circuits apply a proportional gain and an integral gain to an error signal, and the combiner combines both gained error signals to provide a control signal. The limit circuit applies a limit function that limits the proportional gain to a magnitude. The gain booster circuit increases gain while the limit function is being applied. The increased gain may be applied to only the integral gain, or to both the integral and proportional gains such as by boosting gain of the error signal. The apparatus may be a regulator that may include multiple control loops providing multiple error signals, in which a mode selector selects one of the error signals to control regulation. The limit function increases stability while the boosted gain improves transient response during mode transitions.

Abstract: The system and method creates a substantially constant output voltage ripple in a buck converter in discontinuous conduction mode by varying the on-time of a pulse width modulator (PWM) signal driving the buck converter when the buck converter is operating in discontinuous conduction mode. A first signal is generated that is a function of the switching frequency of the buck converter. This signal is low-pass filtered and compared with a second signal that is a function of the switching frequency of the buck converter when operating in continuous conduction mode and with constant PWM on-time. The output signal generated by the comparator is a signal that is equal to the ratio of the first signal and the second signal. The on-time of a voltage controlled oscillator is controlled by the output signal, the oscillator signal causing the on-time of the PWM signal to vary in a controlled fashion.

Abstract: On embodiment pertains to an apparatus including a control loop configured to receive an output voltage sense signal. The control loop includes a compensator; a PWM signal generator coupled to an output of the compensator; a reference circuit configured to receive a tracking signal, and which is configured to low bandwidth low pass filter the tracking signal when the tracking signal amplitude becomes substantially constant and representative of an output voltage that is substantially non-zero, and an error amplifier having a first input coupled to an output of the reference circuit, a second input configured to receive the output voltage sense signal, and an output coupled to the compensator.

Abstract: An enhanced ESD clamp is provided with a resistor connected between the body terminal and the source terminal of a MOSFET device. In one exemplary embodiment, the MOSFET device is a grounded-gate NMOS (ggNMOS) transistor device with the resistor (“body resistor”) connected externally to the MOSFET device. In another embodiment, the MOSFET device is a ggPMOS transistor device. In yet another embodiment, the body resistor is disposed within and connected internally to the MOSFET device. In any event, the resistance value of the body resistor determines the level to which the trigger voltage of the ESD clamp will be reduced when an ESD event occurs.

Abstract: Body contact layouts for semiconductor structures are disclosed. In at least one exemplary embodiment, a semiconductor structure comprises: a plurality of gates disposed on a semiconductor layer, each gate extending parallel to a y-axis in a coordinate space; a source region disposed between two of the plurality of gates; a plurality of body contacts disposed in each source region; and wherein a portion of each source region, adjacent to the gate, has a width extending parallel to the y-axis that is greater than the width of the source region parallel to the y-axis at a distance on an x-axis from the gate.

Abstract: An embodiment of a circuit includes a circuit module and an inductor disposed over and electrically coupled to the module. Disposing the inductor over the module may reduce the area occupied by the circuit as compared to a circuit where the inductor is disposed adjacent to the module, or to a circuit where the inductor is disposed in the module adjacent to other components of the module. Furthermore, disposing the inductor outside of the module may allow one to install or replace the inductor.

Abstract: A voltage error signal is provided to a PWM controller of a voltage regular and used to produce a PWM signal that drives a power stage of the regulator. When operating in an adapter current limit regulation mode, an adapter current sense voltage, indicative of an adapter current, is compared to an adapter current reference voltage to produce an adapter current error signal. A compensator receives the adapter current error signal and outputs a compensated adapter current error signal. The adapter current sense voltage, or a high pass filtered version thereof, is subtracted from the compensated adapter current error signal to produce the voltage error signal provided to the PWM controller. Alternatively, an input voltage, or a high pass filtered version thereof, is added to the compensated adapter current error signal to produce the voltage error signal.