Abstract: A controller configurable to operate in either in an NVDC mode or a standard mode. The controller includes mode logic that detects a mode value indicative of the selected mode and that asserts a corresponding mode signal, and control logic that is configured to operate according to the selected battery charging mode based on the mode signal and that provides a control signal accordingly. In the standard mode, the control signal is in either an on or off state depending upon presence of an external adapter and the charge state of the battery. In the NVDC mode, the control signal may operate in a linear mode if the battery is deeply discharged. A battery detector provides a battery indication that is used to switch the regulation operating point of an external system voltage. A power monitor output provides an indication of power being provided via the system voltage.

Abstract: An optical proximity detector includes a plurality photodetectors (PDs) and a winner-take-all (WTA) circuit. Each of the PDs has a respective field of view (FOV) and produces a respective analog current detection signal indicative of light incident on and detected by the PD. In an embodiment, the WTA circuit includes a comparator and a multiplexor (MUX). The comparator compares the analog current detection signals produced by the PDs and produces a selection signal in dependence thereon. The MUX receives the analog current detection signals produced by the PDs and outputs one of the analog current detection signals in dependence on the selection signal produced by the comparator. Circuitry, which is shared by the PDs, produces a digital detection signal corresponding to the one of the analog current detection signals output by the MUX. Such design can be used to reduce power consumption, size and cost of an optical proximity detector.

Abstract: A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.

Abstract: An integrated circuit comprises a control input providing a connection to a capacitor. A delay circuit generates a delayed enable signal responsive to a provided enable signal. A second circuit performs a control function. A switching circuit responsive to the delayed enable signal connects the control input to the delay circuit in a first mode of operation and connects the control input to the second circuit in a second mode of operation.

Abstract: An equivalent series inductance (ESL) cancel circuit for a regulator for adjusting a feedback voltage by attenuating a magnitude of a square wave ripple voltage developed on an output voltage. The regulator includes an output inductor and an output capacitor, in which the capacitor has an ESL which forms an inductive voltage divider with the output inductor causing the square wave voltage ripple. The ESL cancel circuit may include first and second current sources and a resistor device coupled between the output node and an adjust node which is further coupled to a feedback input of the regulator. The first current source applies a current proportional to the output voltage to the adjust node. The second current source selectively applies a current proportional to the input voltage of the regulator based on a state of the pulse control signal.

Abstract: Embodiments described herein relate to a packaged component including a lead frame and a non-conductive plug disposed between two or more adjacent sections of the lead frame. The plug is composed of a non-conductive material and is adhered to the two or more adjacent sections of the lead frame. The plug functions to impede the flow of solder along edges of the two or more adjacent sections during second level solder reflow events that occur after encapsulation of the packaged component. The plug includes a main portion disposed within a space between the two or more adjacent sections, and one or more overlap portions extending from the main portion. The one or more overlap portions are disposed on an internal surface of at least one of the two or more adjacent sections. At least one component is mounted on one of the plurality of sections of the lead frame.

Abstract: A semiconductor structure for enhanced ESD protection is disclosed. The semiconductor structure includes a plurality of fingers, wherein each finger of the plurality of fingers includes a plurality of voltage clamps, and each voltage clamp of the plurality of voltage clamps includes at least a first well having a first conductivity type and a second well having a second conductivity type, and a connection between a well tie of the first well of a first voltage clamp of the plurality of voltage clamps and a well tie of the first well of a second voltage clamp of the plurality of voltage clamps, wherein the connection is enabled to couple a bias voltage associated with a current flow in the first voltage clamp to the second voltage clamp, and the first voltage clamp and the second voltage clamp are thereby enabled to trigger on substantially simultaneously.

Abstract: Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package, the lead frame having a paddle comprising a step-out bottom locking feature profile across at least a first segment of an edge of the paddle that provides an interface with a mold compound; etching the paddle to have at least a second segment of the edge having either an extended-step-out bottom locking feature profile or an overhanging top locking feature profile; and alternating first and second segments along the edge of the paddle.

Abstract: A universal serial bus charger comprises a universal serial bus connector for providing a connection to a voltage source. An output voltage connector provides a charging voltage to a connected battery. A switching voltage regulator generates the charging voltage responsive to the voltage source. Control circuitry monitors an actual charging current applied to the connected battery and provides a programmed current signal enabling the actual charging current to operate at a programmed level if the actual charging current does not exceed a programmed charging current level. The control circuitry provides a charging current limit signal enabling the actual charging current to operate at a predetermined charge current limit if the actual charging current exceeds the programmed charging current level. PWM control circuitry generates switching control signals to control operation of the switching voltage regulator responsive to the control circuitry.

Abstract: A novel framing method for a variable net bit rate digital communications system that utilizes a set of different QAM constellations and punctured trellis code combinations, each combination designated as a mode. This frame structure has a variable integral number of QAM symbols per frame depending on the selected mode, but the number of bytes and Reed-Solomon packets per frame is constant. This is achieved even though the number of data bits per QAM symbol for some modes is fractional. Also the number of trellis coder puncture pattern cycles per frame is an integer for all modes. This arrangement simplifies the synchronization of receiver processing blocks such as the Viterbi decoder, de-randomizer, byte de-interleaver, and Reed-Solomon decoder.

Abstract: An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a first semiconductor substructure over a semiconductor substrate, forming a first spacer layer over the first semiconductor substructure and the semiconductor substrate, and forming a second semiconductor substructure over at least a portion of the first spacer layer.

Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.

Abstract: A controller for controlling operation of a switching regulator including a modulator, a discontinuous conduction mode (DCM) controller, an audible DCM (ADCM) controller, and a sub-sonic discontinuous conduction mode (SBDCM) controller. The modulator generally operates in a continuous conduction mode. The DCM controller modifies operation to DCM during low loads. The ADCM controller detects when the switching frequency is less than a super-sonic frequency threshold and modifies operation to maintain the switching frequency at a super-sonic frequency level. The SBDCM controller detects a sub-sonic operating condition during ADCM operation and responsively inhibits operation of the ADCM mode controller to allow a SBDCM mode within a sub-sonic switching frequency range. The SBDCM operating mode allows for efficient connected standby operation. The SBDCM controller allows operation to return to other modes when the switching frequency increases above the sub-sonic level.

Abstract: Systems and methods for digital voltage compensation in a power supply integrated circuit are provided. In at least one embodiment, a method includes receiving a digital voltage code, the digital voltage code corresponding to an output voltage value; setting an output count on a first counter to change from a present first digital count corresponding to a present voltage code value toward a target first digital count corresponding to a new voltage code value; and setting a second count to an offset count value on a second counter when the new voltage code value is received. The method also includes combining the second count with the output count to form a combined count value; and decrementing the second count value from the offset count value to zero when the first counter reaches the target first digital count.

Abstract: An image processing apparatus or camera system comprises an image sensor 1, a geometrical position calculation device 6 for performing predetermined correction of a distortion, a first address table 10 for storing information correlating an input side address based on the calculation results of the geometrical position calculation device 6 to an output side address as a reference, a sort unit 11 for sorting the output side addresses according to the input side addresses, a second address table 12 for storing information correlating the output side address to the sorted input side address as a reference, and an address matching device 13 for matching the input side address of input side image data DI with the input side address stored in the second address table 12 and outputting output side image data DO.

Abstract: An optical sensor, according to an embodiment of the present invention, includes a photodetector region and a plurality of slats over the photodetector region. In an embodiment, the slats are made of an opaque polymer material, such as an opaque photoresist. In an embodiment, the slats are angled relative to a surface of the photodetector region.

Abstract: An apparatus for sensing an input current through an inductor includes an RC circuit connected in parallel with the inductor across first and second input pins of an integrated circuit. A voltage monitoring circuit monitors a first voltage at the first input pin of the integrated circuit and monitors a second voltage at the second input pin of the integrated circuit. An op-amp compares the first voltage with the second voltage and generates a control output responsive to the comparison. A current sink circuit responsive to the indication controls the first voltage to substantially equal the second voltage.

Abstract: An optoelectronic apparatus includes one or more packaged optoelectronic semiconductor devices (POSDs), each including one or more optoelectronic elements encapsulated by a light transmissive molding compound. Each POSD includes a top surface formed by a top surface of the light transmissive molding compound that encapsulates the one or more optoelectronic elements of the POSD. Each POSD also includes a bottom surface including electrical contacts for the one or more optoelectronic elements of the POSD. A peripheral surface extends between the top and bottom surfaces. A light reflective molding compound surrounds the peripheral surface of each POSD and forms a reflector cup for each POSD. The electrical contacts on the bottom surface of each POSD are exposed, and thus, are accessible for electrical connections to other circuitry. Where the optoelectronic apparatus includes a plurality of POSDs, the light reflective molding compound also connects neighboring POSDs to one another.

Abstract: A drive control circuit generates switching drive signals for a single phase of a multiphase voltage regulator. A driver circuitry generates the switching drive signals for the voltage regulator responsive to a clock signal. A clock circuitry generates the clock signal responsive to a monitored external clock signal. A phase number detector determines a number of active phases in the multiphase voltage regulator in real time responsive to an indicator on a phase number input monitored by the phase detector.

Abstract: In accordance with an embodiment of the invention, there is an integrated circuit device having a complementary integrated circuit structure comprising a first MOS device. The first MOS device comprises a source doped to a first conductivity type, a drain extension doped to the first conductivity type separated from the source by a gate, and an extension region doped to a second conductivity type underlying at least a portion of the drain extension adjacent to the gate. The integrated circuit structure also comprises a second complementary MOS device comprising a dual drain extension structure.