Abstract: A method of regulating voltage with a switching regulator is disclosed. The method includes sensing an output voltage provided by the regulator. If the output voltage drops below a low voltage threshold, a burst of one or more current pulses is provided. If the output voltage raises above a high voltage threshold during the burst, discontinuing the burst of current pulses. The method includes counting a number of the one or more current pulses in the burst, and comparing the number of the one or more current pulses with at least one pulse threshold. The upper current threshold is adjusted based on the number of the one or more current pulses.

Abstract: In an embodiment, a power-supply controller includes switching circuitry and an adjuster circuit. The switching circuitry is configured to cause a charging current to flow until the charging current has a predetermined relationship to a threshold, and to cause a discharging current to flow to an output node that carries an output voltage after the charging current. And the adjuster circuit is configured to adjust the threshold such that a ripple voltage superimposed on the output voltage has an approximately constant magnitude. For example, a power supply may include such a power-supply controller to maintain the magnitude of the output ripple voltage within a particular range during a pulse-frequency-modulation (PFM) mode despite variations in one or more parameters such as input voltage, output voltage, filter capacitance, phase inductance, and charging-current-sense impedance, from their respective nominal values.

Abstract: A scanning projector system includes a controller, a driver and one or more micro-mirror(s). The controller produces first, second and third pixel data in dependence on a video signal. The driver drives first, second and third light emitting elements in dependence on the first, second and third pixel data produced by the controller, to thereby emit light of first, second and third colors. The micro-mirror(s) project an image in dependence on light beams produced in dependence on the light of the first, second and third colors. To reduce color shifts due to inter-pixel interference, the controller and/or driver causes at least one timing guard band per pixel period associated with each instance of the pixel data.

Abstract: A multi-channel LED driver includes a plurality of linear current regulators, each connected to a bottom of a string of series connected LEDs of a multi-channel LED that controls a bias current and the string of series connected LEDs responsive to an LED bias reference voltage. A dynamic headroom regulation voltage control circuit monitors the headroom regulation voltage at the bottom of each string of the series connected LEDs in the multi-channel LED and generates a reference voltage controlling each of the headroom regulation voltages responsive to the LED bias reference voltage.

Abstract: Embodiments of the present invention relate to systems, devices and methods for translating I2C addresses. In accordance with an embodiment, a method for translating an I2C address includes receiving an original I2C address from a first I2C compatible device via an I2C-bus to which the first I2C compatible device is connected. The method also includes translating the original I2C address to a translated I2C address, and outputting the translated I2C address to a second I2C compatible device via a secondary side of the I2C-bus to which the slave device is connected. The original I2C address can be translated to the translated I2C address by subtracting an offset value from (or adding an offset value to) the original I2C address to produce the translated I2C address. Such an offset value can be specified using pin strapping, or by storing the offset value in a register or non-volatile memory that is programmable via the—I2C bus.

Abstract: An electronic system, a reduced-noise reference voltage platform for a voltage converter device, and a method of manufacture of a reduced-noise reference voltage platform for a voltage converter device are disclosed. For example, the reduced-noise reference voltage (e.g., ground) platform includes a first conductor unit, a second conductor unit, and an insulator unit interposed between a first surface of the first conductor unit and a first surface of the second conductor unit. The reduced-noise reference voltage platform also includes a phase terminal connected to the first conductor unit, and a reference voltage (e.g., ground) terminal connected to the second conductor unit, wherein a second surface of the second conductor unit forms a platform coupled to the reference voltage (e.g., ground).

Abstract: A method for wafer level fabricating a plurality of optoelectronic devices, starting with a wafer that includes a plurality of light detector sensor regions, includes attaching each of a plurality of light source dies to one of a plurality of bond pads on a top surface of the wafer that includes the plurality of light detector sensor regions. The method also includes attaching, to the wafer, a preformed opaque structure made off-wafer from an opaque material, wherein the preformed opaque structure includes opaque vertical optical barriers. Additionally, solder balls or other electrical connectors are attached to the bottom of the wafer. The wafer is diced to separate the wafer into a plurality of optoelectronic devices, each of which includes at least one of the light detector sensor regions, at least one of the light source dies and at least two of the solder balls or other electrical connectors.

Abstract: An optical proximity sensor comprises a light detector die including a light detector sensor area and at least one bond pad on a portion of the light detector die not including the light detector sensor area. A light source die, including anode and cathode terminals, is attached to a portion of the light detector die not including the light detector sensor area, such that at least one of the terminals of the light source die, on a bottom of the light source die, is attached to at least one of the bond pads on the light detector die. An opaque barrier, formed off-wafer relative to a wafer including the light detector die, is attached to and extends upward from a top surface of the light detector die between the light detector sensor area and the light source die. Electrical connectors are on the bottom of the light detector die.

Abstract: A scanning projector system includes a controller, a driver and one or more micro-mirror(s). The controller produces first, second and third pixel data in dependence on a video signal. The driver drives first, second and third light emitting elements in dependence on the first, second and third pixel data, to thereby emit light of first, second and third colors. The micro-mirror(s) project an image in dependence on light beams produced in dependence on the light of the first, second and third colors. The controller controls intensities of the light emitted by the light emitting elements, at least in part, by controlling duty-cycles of pulses included in pixel periods associated with the first, second and third drive signals. To reduce color shifts, the controller and/or the driver causes at least two pulses to be included in each pixel period associated with drive signals used to drive the light emitting elements.

Abstract: A scanning projector system includes a controller, a driver and one or more micro-mirror(s). The controller produces first, second and third pixel data in dependence on a video signal. The driver drives first, second and third light emitting elements in dependence on the first, second and third pixel data produced by the controller, to thereby emit light of first, second and third colors. The micro-mirror(s) project an image in dependence on light beams produced in dependence on the light of the first, second and third colors. To reduce color shifts due to inter-pixel interference, the controller and/or driver causes at least one timing guard band per pixel period associated with each instance of the pixel data.

Abstract: A system, circuit and method for converting a differential voltage signal including a high common mode voltage component to a ground referenced signal are disclosed. For example, a circuit for converting a differential voltage signal including a high common mode voltage component to a ground referenced signal is disclosed. The circuit includes a comparator configured to receive a differential voltage signal including a high common mode voltage component, and output a digital signal associated with the differential voltage signal. The circuit also includes a level shifter configured to receive the digital signal and shift the level of the digital signal to a low level, and an integrator configured to receive the digital low level signal and output a ramping voltage associated with the low level signal. Furthermore, the circuit includes an analog-to-digital converter configured to receive the ramping voltage and output a digital bit-stream associated with the ramping voltage.

Abstract: An adjustable current-synthesizer may generate synthesized current representative of an actual current, according to a model of a circuit that produces the actual current. The current synthesizer may under-sample a current sense signal derived from the actual current to obtain a few samples of the actual current, which are then used to adjust the synthesized current, thereby ensuring accuracy of the synthesized current. Sample values of the actual current are compared with corresponding generated values of the synthesized current to obtain offset values. In order to maintain monotonicity in the synthesizer results, the offset values are used to make adjustments to the slope of the synthesized current. The slope of the synthesized current may also be adjusted according to the slope of the actual current. Sub-Nyquist sampling of the actual current may be performed on the down-slope, with up-slope adjustments made based on the offset adjustment and down-slope adjustment.

Abstract: A system and method capable of injection locking the phases of a peak-valley multiphase regulator includes comparing an output voltage error signal with a ramp control signal and providing a corresponding slope reset signal, using transitions of the slope reset signal to develop a equally spaced high side ramp signals and equally spaced low side ramp signals, and injecting a corresponding one of the high side signals and a corresponding one of the low side ramp signals into each of the phases which correspondingly develop equally spaced pulse control signals for multiphase operation. Such injection locking allows the additional phases to operate out of phase with the first phase and allows operation at high duty cycles.

Abstract: An apparatus for charging a plurality of series connected battery cells, includes a first and second input terminals for providing a charging voltage to the plurality of series connected battery cell. A transformer includes a primary side associated with the charging voltage and a secondary side includes a plurality of portions. Each of the plurality of portions is connected across at least one of the plurality of series connected battery cell. A switch in series between each of the plurality of portions of the secondary side and the at least one of the plurality of series connected battery cells increases an impedance between the portion of the secondary side and the associated one of the plurality of series connected battery cells in a first state and decreases the impedance between the portion of the secondary side and the associated one of the plurality of series connected battery cells in a second state.

Abstract: Systems, semiconductor structures, electronic circuits and methods for enhanced transient response in Low Dropout (LDO) voltage regulators are disclosed. For example, a semiconductor structure for enhanced transient response in an LDO voltage regulator is disclosed, which includes a first current mirror circuit coupled to an input connection and an output connection of the LDO voltage regulator, a second current mirror circuit coupled to the input connection of the LDO voltage regulator. A first input of a first amplifier circuit is coupled to the second current mirror circuit, a second input of the first amplifier circuit is coupled to the output connection of the LDO voltage regulator, and a third input of the first amplifier circuit is coupled to a reference voltage.

Abstract: A folded cascode amplifier (FCA) including cascode stages coupled in a stacked cascode configuration, an input stage, and a switch circuit. The stages may include first and second P-type stages and first and second N-type stages, in which the first N-type stage and the input stage receive first and second bias voltages, respectively. The switch circuit couples a first cascode bias voltage to the second P-type stage and couples a second cascode bias voltage to the first N-type stage in a high power state, and decouples the first and second cascode bias voltages in a low power state. A non-switched low current bias generator provides the first and second bias and cascode bias voltages, which remain substantially stable in the low and high power states. Only low parasitic capacitance nodes are switched between power states so that the gain of the FCA recovers very quickly for the high power state.

Abstract: A circuit and method for switching between a system's internal clock and an external synchronization clock when a stable external clock has been detected, and for switching back to operating the system using said internal clock when a predetermined number of sequential external clock pulses exceed a predetermined switching period dropout threshold or are otherwise missing.

Abstract: A modulator for controlling a switch circuit of a voltage regulator, including a sense circuit that provides a current sense signal indicative of current through the output inductor, a ramp circuit that develops a ramp voltage on a ramp node using the current sense signal, an error circuit that develops an error signal indicative of output voltage error and that injects the error signal into the ramp node to adjust the ramp voltage, a comparator circuit that compares the ramp voltage with a fixed control voltage to develop a compare signal, and a logic circuit that uses the compare signal to develop a pulse control signal that controls the switch circuit. The output voltage error may be determined by comparing the output voltage with a reference voltage and converting the error voltage to a current applied to the ramp node.

Abstract: A controller, for use with an SMPS DC-DC converter, includes a PWM/PFM generator and a switch driver. The PWM/PFM generator simultaneously generates CTRLPWM and CTRLPFM signals in dependence on a CTRL signal. The switch driver generates a drive signal in dependence on both the CTRLPWM and CTRLPFM signals. The drive signal is used to control a power switch of the DC-DC converter. The CTRL signal is generated in dependence on a feedback signal indicative of an output voltage or current of the DC-DC converter. Regardless of the mode of the DC-DC converter, the CTRLPWM signal is used to control a peak current in an inductor of the DC-DC converter, and the CTRLPFM signal is used to control a switching frequency of the power switch. In certain embodiments, both the CTRLPFM and CTRLPWM signals are varied in dependence on the feedback signal when the DC-DC converter is in a PWM-PFM mode.

Abstract: An apparatus includes a buck boost converter for generating a regulated output voltage responsive to an input voltage. The buck boost converter includes an inductor, a first pair of switching transistors responsive to a first PWM signal and a second pair of switching transistors responsive to a second PWM signal. An error amplifier generates an error voltage responsive to the regulated output voltage and a reference voltage. A control circuit generates the first PWM signal and the second PWM signal responsive to the error voltage and a sensed current voltage responsive to a sensed current through the inductor. The control circuit controls switching of the first pair of switching transistors and the second pair of switching transistors using the first PWM signal and the second PWM signal responsive to the sensed current through the inductor and a plurality of offset error voltages based on the error voltage.