Abstract: A circuit can compensate for intra pair skew or mode conversion in a channel by applying a second or corrective mode conversion effect that counters the channel's mode conversion. The circuit can process the common mode signal with a frequency dependent filter prior to injection back into the differential mode. The circuit can implement the reverse mode conversion with passive circuits using integrated resistors and metal oxide semiconductor (MOS) switches. In certain embodiments, such actions can proceed effectively without necessarily consuming active power.

Abstract: An electronic system, a reduced-noise reference voltage platform for a voltage converter device, and a method of manufacture of a reduced-noise reference voltage platform for a voltage converter device are disclosed. For example, the reduced-noise reference voltage (e.g., ground) platform includes a first conductor unit, a second conductor unit, and an insulator unit interposed between a first surface of the first conductor unit and a first surface of the second conductor unit. The reduced-noise reference voltage platform also includes a phase terminal connected to the first conductor unit, and a reference voltage (e.g., ground) terminal connected to the second conductor unit, wherein a second surface of the second conductor unit forms a platform coupled to the reference voltage (e.g., ground).

Abstract: Light sensors including dielectric optical coatings to shape their spectral responses, and methods for fabricating such light sensors in a manner that accelerates lift-off processes and increases process margins, are described herein. In an embodiment, a light sensor includes a photodetector sensor region formed in a semiconductor substrate, a dielectric optical coating filter covering the photodetector sensor region, and dummy dielectric optical coating features beyond the photodetector sensor region, wherein the dummy dielectric optical features include one or more dummy corners, dummy islands and/or dummy rings. Alternatively, or additionally, the dielectric optical coating filter includes chamfered corners, which improves the thermal reliability of the dielectric optical coating.

Abstract: A modulator with balanced slope compensation including a control network, a slope compensation network, an offset network and an adjust network. The control network receives a feedback signal indicative of an output voltage and provides a loop control signal. The slope compensation network develops a slope compensation signal. The offset network determines a DC offset of the slope compensation signal. The adjust network combines the DC offset, the slope compensation signal and the loop control signal to provide a balanced slope compensated control signal. The DC offset may be determined as a peak of the slope compensation signal. The slope compensation signal may be developed based on the output voltage and a pulse control signal, in which the pulse control signal is developed using the balanced slope compensated control signal.

Abstract: One embodiment is directed towards a packaged chip including a lead frame. At least one chip is mounted on the lead frame. At least one edge the lead frame has a solder flow impeding feature located thereon. The solder flow impeding feature includes an integral portion of the lead frame that extends in a first projection outward at an edge of the lead frame and parallel to an external surface of the lead frame. An internal surface of the first projection is aligned with an internal surface of the main portion of the lead frame. The solder flow impeding feature also includes a second projection that extends from an external side of the first projection in a direction generally perpendicular to the first projection.

Abstract: A voltage regulator integrated circuit comprises a control circuit driving at least one power switch to provide a regulated voltage at an output of an inductor/capacitor (LC) circuit coupled to the at least one power switch; an error amplifier having a first input coupled to a feedback signal representative of the regulated output voltage and a second input coupled to a reference signal; and a compensation network coupled to an output of the error amplifier and configured to provide a compensation voltage. The compensation network includes at least one digitally programmable resistor array and at least one digitally programmable capacitor array. Each array provides a plurality of user selectable component values. The control circuit includes a pulse modulator configured to modulate an input voltage based on the compensation voltage.

Abstract: Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.

Abstract: A DMT system for a half-duplex two-way link carries Internet protocol encoded video stream on a coaxial cable that also carries a baseband rendition of the same video stream. A plurality of downlink symbols modulated on a subband of subcarriers in a downlink signal are decoded. The symbols may carry data encoded on a subband using a constellation of QAM symbols assigned to the subband. Other subbands may be associated with different QAM constellations. Lower-order constellations of QAM symbols may be assigned to subbands that include higher-frequency subcarriers and higher-order constellations of QAM symbols may be assigned to subbands that include lower-frequency subcarriers. A block error correction decoder may be synchronized based on an identification of the first constellation of QAM symbols and information identifying boundaries between the plurality of downlink symbols.

Abstract: An optical sensor includes a driver, light detector and echo canceller. The driver is adapted to selectively drive a light source. The light detector is adapted to produce a detection signal indicative of an intensity of light detected by the light detector. The echo canceller is adapted to produce an echo cancellation signal that is combined with the detection signal produced by the light detector to produce an echo cancelled detection signal having a predetermined target magnitude (e.g., zero). The echo canceller includes a coefficient generator that is adapted to produce echo cancellation coefficients indicative of distance(s) to one or more objects, if any, within the sense region of the optical sensor. The optical sensor can also include a proximity detector adapted to detect distance(s) to one or more objects within the sense region of the optical sensor based on the echo cancellation coefficients generated by the coefficient generator.

Abstract: A signal filter and accompanying methods. In one embodiment, the filter includes a first mechanism for receiving a first signal. A second mechanism employs one or more modified representations of the first signal to cancel one or more frequency components of the first signal, yielding an output signal in response thereto. In a more specific embodiment, the first mechanism includes a splitter for receiving the first signal and splitting the first signal onto a first path and a second path. The second mechanism further includes one or more delay modules and one or more phase shifters in the first path and/or the second path. One or more controllable amplifiers are optionally included in the first path and/or the second path. The one or more delay modules, phase shifters, or amplifiers are responsive to one or more control signals from a controller. The controller is adapted to modify behavior of the second mechanism so that the filter is characterized by a desired frequency response.

Abstract: Packaged light detector semiconductor devices (PLDSDs), methods for manufacturing PLDSDs, and systems including a PLDSD are described herein. In an embodiment, a PLDSD includes a light detector die having a surface including an active photosensor region, and a non-imaging optical concentrator including an entrance aperture and an exit aperture axially aligned with one another and with the active photosensor region. A molding material forms the non-imaging optical concentrator and encapsulates at least a portion of the surface of the light detector die that extends beyond the exit aperture of the non-imaging optical concentrator. The non-imaging optical concentrator concentrates light from the entrance aperture toward the exit aperture and onto the active photosensor region.

Abstract: An electronic circuit (EC) may include an integrated current-source with an output terminal that may couple to the output of a power converter (OPC) to draw current from the power converter. The EC may further include control circuitry for activating the integrated current-source and for effecting a ramping output voltage at the OPC, and begin current-sense calibration once the output voltage reaches a specified calibration voltage value (SCVV). The control circuitry may regulate the output voltage to the SCVV while current-sense calibration is being performed, to measure and store the resistance value of a current-sense element of the power regulator. With the current-sense calibration complete, the control circuitry may disable the integrated current-source, resume ramping the output voltage until it reaches a specified regulation value (SRVV), and regulate to the SRVV during normal operation. The SCVV is specified to be at least a magnitude lower than the SRVV.

Abstract: A buck/boost voltage regulator generates a regulated output voltage responsive to an input voltage and a plurality of control signals. The buck/boost voltage regulator includes a plurality of switching transistors responsive to the plurality of control signals. Control circuitry monitors the regulated output voltage and generates the plurality of control signals responsive thereto. The control circuitry controls the operation of the plurality of switching transistors to enable a charging phase in a first mode of operation, a pass through phase in a second mode of operation and a discharge phase in a third mode of operation within the buck/boost voltage regulator to eliminate occurrence of a four switch switching condition.

Abstract: A feedback control system, e.g. a voltage regulator, may include a control stage controlling an output stage that generates an output. The control stage may generate a control signal, e.g. a pulse-width modulated signal, having a duty-cycle and a switching frequency, and adjust the switching frequency when a present value of the duty-cycle differs from a most recent previous value of the duty-cycle, until the duty-cycle starts increasing, while also adjusting the duty-cycle according to the output. By adjusting the switching frequency, the (power) efficiency of the system may be optimized also regulating the output. The feedback system may also adjust the switching frequency according to an alternate algorithm to improve but not necessarily optimize the power efficiency by scaling a programmed frequency value using a scaling factor that is a function of a maximum duty-cycle value, a present frequency value, the programmed frequency value, and a minimum frequency value.

Abstract: A system and method capable of injection locking the phases of a peak-valley multiphase regulator includes comparing an output voltage error signal with a ramp control signal and providing a corresponding slope reset signal, using transitions of the slope reset signal to develop a equally spaced high side ramp signals and equally spaced low side ramp signals, and injecting a corresponding one of the high side signals and a corresponding one of the low side ramp signals into each of the phases which correspondingly develop equally spaced pulse control signals for multiphase operation. Such injection locking allows the additional phases to operate out of phase with the first phase and allows operation at high duty cycles.

Abstract: An equivalent series inductance (ESL) cancel circuit for a regulator for adjusting a feedback voltage by attenuating a magnitude of a square wave ripple voltage developed on an output voltage. The regulator includes an output inductor and an output capacitor, in which the capacitor has an ESL which forms an inductive voltage divider with the output inductor causing the square wave voltage ripple. The ESL cancel circuit may include first and second current sources and a resistor device coupled between the output node and an adjust node which is further coupled to a feedback input of the regulator. The first current source applies a current proportional to the output voltage to the adjust node. The second current source selectively applies a current proportional to the input voltage of the regulator based on a state of the pulse control signal.

Abstract: A controller, for use with an SMPS DC-DC converter, includes a PWM/PFM generator and a switch driver. The PWM/PFM generator simultaneously generates CTRLPWM and CTRLPFM signals in dependence on a CTRL signal. The switch driver generates a drive signal in dependence on both the CTRLPWM and CTRLPFM signals. The drive signal is used to control a power switch of the DC-DC converter. The CTRL signal is generated in dependence on a feedback signal indicative of an output voltage or current of the DC-DC converter. Regardless of the mode of the DC-DC converter, the CTRLPWM signal is used to control a peak current in an inductor of the DC-DC converter, and the CTRLPFM signal is used to control a switching frequency of the power switch. In certain embodiments, both the CTRLPFM and CTRLPWM signals are varied in dependence on the feedback signal when the DC-DC converter is in a PWM-PFM mode.

Abstract: In an embodiment, an apparatus, such as a power-supply controller, includes a generator and an adjuster. The generator is configured to provide a switching signal that causes a power supply to generate a regulated output signal, and the adjuster is configured to impart a condition to the power supply while the power supply is operating in a first mode, the condition being approximately equal to a condition that the power supply would have if the power supply were operating in a second mode. For example, such an apparatus may be able to reduce or eliminate a transient on a regulated output signal (e.g., a regulated output voltage) when a power supply transitions from a first operating mode, such as a pulse-frequency-modulation (PFM) mode, to a second operating mode, such as a pulse-width-modulation (PWM) mode.

Abstract: Embodiments described herein relate to a method of manufacturing a packaged circuit having a solder flow-impeding plug on a lead frame. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch forming a trench. A non-conductive material that is adhesive to the lead frame is applied in the trench, such that the non-conductive material extends across the trench to form the solder flow-impeding plug. One or more components are attached to the internal surface of the lead frame and encapsulated. An external surface of the lead frame is etched at the dividing lines to disconnect different sections of lead frame as a second partial etch.

Abstract: Systems and methods for providing a full fail-safe capability in signal transmission networks are disclosed. For example, a system for providing a full fail-safe capability in signal transmission networks includes at least a first electronic circuit to transmit and receive signals or data, at least one driver unit coupled to the at least a first electronic circuit, and at least one receiver unit coupled to the at least a first electronic circuit and the at least one driver unit. The at least one receiver unit includes at least one offset signal generating unit, a signal comparing unit, and a switching unit to couple an offset signal from the at least one offset signal generating unit to an input of the signal comparing unit.