Patents Assigned to Intersil Americas LLC
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Patent number: 8966294Abstract: A power converter comprises an input port configured to receive a source of power, an output port configured to provide output power, and a bridge circuit coupled to the input port. The bridge circuit comprises a first switch coupled in series with a second switch, and a third switch coupled in series with a fourth switch. A first clamp rectifier is coupled in series with a second clamp rectifier, and the first and second clamp rectifiers are coupled in parallel with the first and second switches. A first clamp capacitor is coupled between the first and second clamp rectifiers, with the first clamp capacitor operative to reduce power loss in the first and second clamp rectifiers. A first resonant inductor is coupled between the first and second switches. The power converter also includes a transformer operatively coupled to the bridge circuit, with the transformer comprising a primary winding and at least one secondary winding.Type: GrantFiled: August 12, 2011Date of Patent: February 24, 2015Assignee: Intersil Americas LLCInventors: Xiaodong (David) Zhan, Long (Robin) Yu, Shijia (Billy) Yang
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Patent number: 8963266Abstract: A device having a detector includes a sensor package. The sensor package includes a light sensor, at least one filter located over the light sensor and at least one bond pad. The light sensor is formed on a semiconductor device that provides sensor information related to light incident upon the light sensor. A perimeter of each bond pad is covered by a protective layer forming a sidewall seal. The sensor package also includes a package that encases the light sensor, filter(s) and bond pad(s). Additionally, at least one package pin is communicatively coupled to the bond pad(s). The device also includes a functional circuit that is coupled to the sensor package and receives the sensor information from the light sensor. The device can be an ambient light sensor, camera, backlit mirror, handheld electronic device, filter device, light-to-digital output sensor, gain selection device, proximity sensor, or light-to-voltage non-linear converter.Type: GrantFiled: June 7, 2012Date of Patent: February 24, 2015Assignee: Intersil Americas LLCInventors: Helen Hongwei Li, Joy Ellen Jones, Phillip J. Benzel, Jeanne M. McNamara, John T. Gasner
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Patent number: 8964863Abstract: Examples disclosed herein provide daisy chain communication system. The daisy chain communication system includes a plurality of transceivers coupled to devices which provide data signals to, and receive data signals from, their one or more coupled transceivers. The transceivers are configured to transmit and receive an amplitude modulated signal having edges corresponding to edges of a clock signal and amplitudes corresponding to a digital value of the first data signal.Type: GrantFiled: August 1, 2014Date of Patent: February 24, 2015Assignee: Intersil Americas LLCInventor: Anthony John Allen
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Patent number: 8963521Abstract: An embodiment of a power supply includes an input node operable to receive an input voltage, an output node operable to provide a regulated output voltage, an odd number of magnetically coupled phase paths each coupled between the input and output nodes, and a first magnetically uncoupled phase path coupled between the input and output nodes. Such a power supply may improve its efficiency by activating different combinations of the coupled and uncoupled phase paths depending on the load conditions. For example, the power supply may activate only an uncoupled phase path during light-load conditions, may activate only coupled phase paths during moderate-load conditions, and may activate both coupled and uncoupled phase paths during heavy-load conditions and during a step-up load transient.Type: GrantFiled: March 28, 2013Date of Patent: February 24, 2015Assignee: Intersil Americas LLCInventors: Jia Wei, Michael Jason Houston
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Patent number: 8957491Abstract: An optical sensor, according to an embodiment of the present invention, includes a photodetector region and a plurality of slats over the photodetector region. In an embodiment, the slats are made up of a plurality of metal layers connected in a stacked configuration with a plurality of metal columns. The metal columns can be made of metal vias, metal contacts and/or metal plugs. In an embodiment, the slats are angled relative to a surface of the photodetector region, wherein the angling of the slats is achieved by the metal layers being laterally offset relative to one another and/or metal columns being laterally offset relative to one another. In an alternative embodiment, the slats are made of an opaque polymer material, such as an opaque photoresist.Type: GrantFiled: December 10, 2013Date of Patent: February 17, 2015Assignee: Intersil Americas LLCInventor: Francois Hebert
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Patent number: 8951847Abstract: Embodiments of a leadframe for a device packaging are used not only for structural support and connectivity to the I/O pins to the external world, but also for housing and/or mounting devices above and below the leadframe. Being electrically conductive, the leadframe also serves as a low resistance interconnect and good current carrier between the bondpads on one device or between the bondpads on different devices above and/or below the leadframe.Type: GrantFiled: September 12, 2012Date of Patent: February 10, 2015Assignee: Intersil Americas LLCInventors: Nikhil Vishwanath Kelkar, Kai Liu
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Patent number: 8946875Abstract: A packaged semiconductor device includes at least first and second lead-fingers. A molded structure forms a cavity and is molded around portions of each of the first and second lead-fingers to thereby mechanically attach each of the first and second lead-fingers to the molded structure. A semiconductor structure (e.g., a IC, chip or die) is attached within the cavity. First and second bond wires respectively providing electrical connections between the semiconductor structure and the first and second lead-fingers. A further portion of each of the first and second lead-fingers is mechanically attached to a bottom surface of the semiconductor structure to inhibit relative mechanical motion between the semiconductor structure, the molded structure and the first and second lead-fingers.Type: GrantFiled: September 27, 2012Date of Patent: February 3, 2015Assignee: Intersil Americas LLCInventors: Nikhil Vishwanath Kelkar, Lynn Wiese, Viraj Ajit Patwardhan
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Patent number: 8946912Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.Type: GrantFiled: December 31, 2013Date of Patent: February 3, 2015Assignee: Intersil Americas LLCInventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty
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Publication number: 20150022921Abstract: A semiconductor structure for enhanced ESD protection is disclosed. The semiconductor structure includes a plurality of fingers, wherein each finger of the plurality of fingers includes a plurality of voltage clamps, and each voltage clamp of the plurality of voltage clamps includes at least a first well having a first conductivity type and a second well having a second conductivity type, and a connection between a well tie of the first well of a first voltage clamp of the plurality of voltage clamps and a well tie of the first well of a second voltage clamp of the plurality of voltage clamps, wherein the connection is enabled to couple a bias voltage associated with a current flow in the first voltage clamp to the second voltage clamp, and the first voltage clamp and the second voltage clamp are thereby enabled to trigger on substantially simultaneously.Type: ApplicationFiled: October 3, 2013Publication date: January 22, 2015Applicant: INTERSIL AMERICAS LLCInventor: James Edwin Vinson
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Patent number: 8907264Abstract: An optoelectronics apparatus selectively drives a light source, and includes four electrically isolated photodetector (PD) segments that detect light that has reflected off an object. Each of the four PD segments produces a corresponding signal, referred to as signals A, B, C and D, indicative of the light detected by the respective PD segment. Circuitry is used to produce a first motion signal indicative of a sum of the signals A plus B minus a sum of the signals C plus D, i.e., the first motion signal is indicative of (A+B)?(C+D). Further circuitry produces a second motion signal indicative of (B+C)?(A+D). Additional circuitry produces a signal and/or data that is indicative of a direction and/or rate of motion of an object, in dependence on the first and second motion signals.Type: GrantFiled: June 14, 2012Date of Patent: December 9, 2014Assignee: Intersil Americas LLCInventor: Allen M. Earman
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Patent number: 8908092Abstract: Methods, systems and devices described herein improve vertical resolution at sides of a four cornered image produced by a scanning projector display device. In accordance with an embodiment, a first plurality of frames (e.g., odd frames) of the image are scanned back and forth from side to side starting at a first line level, in one of the corners. Additionally, a second plurality of frames (e.g., even frames) of the image are scanned back and forth from side to side, starting at a vertical offset level from the first line level, in the same one of the corners. The scanning of the first plurality of frames (e.g., the odd frames) is interleaved with the scanning of the second plurality of frames (e.g., the even frames).Type: GrantFiled: June 28, 2012Date of Patent: December 9, 2014Assignee: Intersil Americas LLCInventors: Morgan Tang, Peter J. Mole, Jayant Vivrekar
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Patent number: 8901832Abstract: An LED driver system including an input receiving a rectified AC conductive angle modulated voltage on a rectified node, a converter, a low-pass filter, and AC detector, and a driver network. The converter is coupled to the rectified node and includes a power switching device coupled to a switching node, in which the power switching device is controlled to convert the rectified AC conductive angle modulated voltage to an output voltage and output current. The low-pass filter is configured to filter voltage of the switching node to provide a filtered voltage. The AC detector receives the filtered voltage and provides a current sense signal indicative thereof. The driver network controls duty cycle of the power switching device based on the current sense signal.Type: GrantFiled: June 28, 2012Date of Patent: December 2, 2014Assignee: Intersil Americas LLCInventors: Weihong Qiu, Rakesh Anumula, Fred F. Greenfeld
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Patent number: 8902346Abstract: Certain embodiments described herein relate to a scanning controller configured produce a horizontal (H) and vertical (V) scanning control signal that is used to control a bi-axial scanning mirror of a scanning laser projector device, a system including such a scanning controller, and a method for generating such an H and V scanning control signal. In an embodiment, the H and V scanning control signal includes H scanning frequency content that is used to control a H scanning frequency of the bi-axial scanning mirror, and V scanning frequency content that is used to control a V scanning frequency of the bi-axial scanning mirror. To avoid cross talk, the scanning controller is configured to produce the H and V scanning control signal such that the H scanning frequency content has a null at DC, and the V scanning frequency content has a null at the H scanning frequency.Type: GrantFiled: February 8, 2013Date of Patent: December 2, 2014Assignee: Intersil Americas LLCInventor: Gwilym Luff
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Patent number: 8901910Abstract: A predictive current feedback system for a switched mode regulator including a sample and hold network for sampling voltage across a lower switch of the regulator and for providing a hold signal indicative thereof, and a predictive current feedback network which adds an offset adjustment to the hold signal based on a duration of a pulse width of a pulse control signal developed by the regulator. Sampling may be done while the lower switch is on for providing a hold value indicative of inductor current while the pulse control signal is low. The offset adjustment may be added to the hold signal in response to a transient event when the pulse signal is high. The offset may be incremental values after each of incremental time periods after a nominal time period, or may be a time-varying value. Adjustment may be made while the pulse signal is low as well.Type: GrantFiled: June 25, 2012Date of Patent: December 2, 2014Assignee: Intersil Americas LLCInventors: Steven P. Laur, M. Jason Houston, Rhys S. A. Philbrick, Thomas A. Jochum
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Patent number: 8890501Abstract: A method for soft-starting a voltage generator includes disabling an output driver; detecting the voltage on an output node; ramping a reference voltage at a controlled rate from a predetermined first level until the reference voltage reaches a second level that is a predetermined function of said output node voltage; enabling the output driver when the reference voltage reaches said second level; and then ramping the reference voltage and the output node voltage at a controlled rate to a boot voltage level. A soft-start circuit for an output voltage generator includes a comparator for causing a ramp generator to ramp the reference voltage and the voltage on the output node to a boot voltage level at a controlled rate once the comparator detects that the reference voltage is substantially equal to the voltage on the output node.Type: GrantFiled: January 26, 2012Date of Patent: November 18, 2014Assignee: Intersil Americas, LLCInventors: Shawn D. Evans, Bogdan M. Duduman, Cindy C. Manion
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Publication number: 20140333270Abstract: Voltage regulators in a current share arrangement may provide a total current to a common load, and may be simultaneously turned on to ramp up member currents. Each voltage regulator may provide a respective member current in the current share configuration. A target current value may be determined from a cycle-averaged current value of the member currents and a voltage error value of the voltage regulator, and each member current may be ramped to the target current value instead of the cycle-averaged current value when the voltage regulators are turned on, resulting in more stable and balanced current ramping. A predictive multi-phase digital controller may therefore operate according to a target current determined based on a measured or inferred inductor current and an error voltage. Pulse-width, pulse position and pulse frequency (adding or skipping pulses) may be calculated according to the operation of the predictive multi-phase digital controller.Type: ApplicationFiled: December 31, 2013Publication date: November 13, 2014Applicant: INTERSIL AMERICAS LLCInventors: Chris M. Young, Sunder S. Kidambi, James R. Toker
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Patent number: 8877564Abstract: One embodiment is directed towards a method of manufacturing a packaged circuit. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch. One or more dies are attached to the internal surface of the lead frame and encapsulated. The method also includes partially etching an external surface of the lead frame at the dividing lines to disconnect different sections of lead frame as a second partial etch, wherein the second partial etch removes a laterally wider portion of the lead frame than the first partial etch of the internal surface; and partially etching the external surface of the lead frame as a third partial etch, wherein the third partial etch overlaps a portion of the second partial etch and extends deeper into the lead frame than the second partial etch.Type: GrantFiled: September 27, 2012Date of Patent: November 4, 2014Assignee: Intersil Americas LLCInventors: Randolph Cruz, Loyde M. Carpenter, Jr.
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Patent number: 8872978Abstract: Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels. One or more values indicative of one or more levels of compensation provided by the equalizer are stored in memory and/or registers for each time, of a plurality of times. A monitor monitors for changes in the cable and/or the video signal transmitted over the cable based on the stored values.Type: GrantFiled: September 9, 2011Date of Patent: October 28, 2014Assignee: Intersil Americas LLCInventors: David W. Ritter, Kathryn M. Tucker
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Patent number: 8871572Abstract: Embodiments described herein relate to manufacturing a device. The method includes etching at least one recess pattern in an internal surface of a lead frame, the at least one recess pattern including a perimeter recess that defines a perimeter of a mounting area. The method also includes attaching a component to the internal surface of the lead frame such that a single terminal of the component is attached in the mounting area and the single terminal covers the perimeter recess, wherein the perimeter recess has a size and shape such that the recess is proximate a perimeter of the single terminal.Type: GrantFiled: December 20, 2012Date of Patent: October 28, 2014Assignee: Intersil Americas LLCInventors: Randolph Cruz, Loyde M. Carpenter, Jr.
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Patent number: 8866453Abstract: A Buck switching regulator includes first Buck switching regulator circuitry is operable to generate a first output voltage from an input voltage and operable to generate a first sensed voltage having a value that is proportional to an output current being provided by the first Buck switching regulator circuitry. The first Buck switching regulator circuitry receives an input current and operates at a first duty cycle determined by a duty cycle signal. Input current sensing circuitry includes second Buck switching regulator circuitry coupled to the first Buck regulator switching circuitry to receive the duty cycle signal and to receive the first sensed voltage as an input voltage to the second Buck switching regulator circuitry. The second Buck switching regulator circuitry is operable responsive to the duty cycle signal to generate a second output voltage from the first sensed voltage.Type: GrantFiled: August 28, 2009Date of Patent: October 21, 2014Assignee: Intersil Americas LLCInventor: Robert L. Lyle, Jr.