Abstract: The present disclosure is related to non-volatile memory devices comprising a reversible resistivity-switching layer used for storing data. The resistivity of this layer can be varied between at least two stable resistivity states such that at least one bit can be stored therein. In particular this resistivity-switching layer is a metal oxide or a metal nitride. A resistivity-switching non-volatile memory element includes a resistivity-switching metal-oxide layer sandwiched between a top electrode and a bottom electrode. The resistivity-switching metal-oxide layer has a gradient of oxygen over its thickness. The gradient is formed in a thermal oxidation step. Set and reset voltages can be tuned by using different oxygen gradients.

Abstract: The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in the reactor where the growth takes place at high temperature, prior cooling down the structure and loading the sample out of the reactor, as well as a method to produce some HEMT transistors on those heterostructures, by depositing the contact on the surface without any removal of the SiN layer by MOCVD. The present invention recites also a device.

Abstract: The disclosed systems and methods relate to floating gate non-volatile memory cells, with a floating gate comprising at least two layers constructed in different conductive or semiconductive materials.

Abstract: A method for determining programming/erase conditions and a method for operating a charge-trapping semiconductor device are disclosed. Programming and erase conditions are determined such that a first net charge distribution variation profile, upon going from programmed to erased state, is substantially the opposite of a second net charge distribution variation profile, upon going from erased to programmed state.

Abstract: A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method comprises providing a first metal layer over a first electrode in a first region, and at least a first work function tuning element. The method further comprises providing a second metal layer of a second metal in a second region at least over a second electrode. The method further comprises performing a first silicidation of the first electrode and a second silicidation of the second electrode simultaneously.

Abstract: A method of managing the operation of a system is presented. The system includes a processing subsystem configured to run a multimedia application and a telecommunication subsystem. The method includes determining telecom environment conditions, and selecting a configuration from a plurality of configurations. The selecting is based at least in part on the determined environmental conditions. The method also includes setting control parameters such as channel speed in the multimedia application and/or the telecommunication subsystem to cause the system to operate at the selected configuration, and operating the system at the selected configuration. The configuration are determined by simultaneously updating control parameters by a controller of both the multimedia application and the telecommunication subsystem.

Abstract: A method for forming catalyst nanoparticles on a substrate and a method for forming elongate nanostructures on a substrate using the nanoparticles as a catalyst are provided. The methods may advantageously be used in, for example, semiconductor processing. The methods are scalable and fully compatible with existing semiconductor processing technology. Furthermore, the methods allow forming catalyst particles and elongate nanostructures at predetermined locations on a substrate.

Abstract: The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 ?.

Abstract: A method and apparatus for removing a first liquid from a surface of a substrate is provided. A second liquid is supplied to at least part of a surface of a substrate having a rotary movement. The rotary movement has a center of rotation and an edge of rotation. The second liquid is directed from the center of rotation to the edge of rotation using a nozzle. A dry zone is created on the substrate as the position of the spray moves from the center of rotation to the edge of rotation. As a result, the first liquid and the second liquid are removed from the surface of the substrate.

Abstract: A method is provided for characterizing an immersion lithography process of a device using an immersion liquid. In order to study pre-soak and post-soak effects on the image performance of an immersion lithography process, the method includes determining at least one image performance characteristic as function of contact times between the immersion liquid and the device for a device illuminated in a dry lithography process and contacted with said immersion liquid prior and/or after said illumination. Based on the image performance characteristic, a lithography process characteristic is derived for the immersion lithography process.

Abstract: The present invention recites a composition comprising a first compound and a second compound. The first compound has the chemical formula ( 1a), wherein m, n and o are independently from each other equal to 2 or 3; wherein p is equal to 1 or 2; R being a chemical group with the chemical formula (1a?), wherein q is equal to 1, 2 or 3; wherein R1, R2 and R3 are independently selected from the group consisting of hydrogen and an organic group. The second compound has the chemical formula (1c). Metal ions can be present in the solution or in an external medium being contacted with the solution. The present invention can be used for cleaning a semiconductor substrate.

Abstract: A method is disclosed for the selective removal of rare earth based high-k materials such as rare earth scandate high-k materials (e.g. DyScO3) over silicon or silicon dioxide. As an example Dy and Sc comprising high-k materials are used as a high-k material in gate stacks of a semiconductor device. The selective removal and etch of this high-k material is very difficult since Dy and Sc (and their oxides) are difficult to etch. The etching could however be easily stopped on them. For patterning of the metal gates comprising TiN and TaN on top of rare earth based high-k layer a chlorine-containing gases (Cl2 and BCl3) can be used since titanium ant tantalum chlorides are volatile and reasonable selectivity to other material present on the wafer (Si, SiO2) can be obtained. The Dy and Sc chlorides are not volatile, but they are water soluble.

Abstract: The present invention discloses a method for forming germanides on substrates with exposed germanium and exposed dielectric(s) topography, thereby allowing for variations in the germanide forming process. The method comprises the steps of depositing nickel on a substrate having topography, performing a first thermal step to convert substantially all deposited nickel in regions away from the topography into a germanide, selectively removing the unreacted nickel, and performing a second thermal step to lower the resistance of formed germanide.

Abstract: The present invention is related to a method of producing a semiconductor device and the resulting device. The method is suitable in the first place for producing high power devices, such as High Electron Mobility Transistors (HEMT), in particular HEMT-devices with multiples source-gate-drain groups or multiple base bipolar transistors. According to the method, the interconnect between the source contacts is not produced by air bridge structures, but by etching vias through the semiconductor layer directly to the ohmic contacts and applying a contact layer on the backside of the device.

Abstract: A technique is described for the preparation of polymers according to a process in which the starting compound of formula (I) is polymerized in the presence of a base in an organic solvent. No end chain controlling agents are required during the polymerisation to obtain soluble precursor polymers. The precursor polymer such obtained comprises structural units of the formula (II). In a next step, the precursor polymer (II) is subjected to a conversion reaction towards a soluble or insoluble conjugated polymer by thermal treatment. The arylene or heteroarylene polymer comprises structural units of the formula III. In this process the dithiocarbamate group acts as a leaving group and permits the formation of a precursor polymer of structural formula (II), which has an average molecular weight from 5000 to 1000000 Dalton and is soluble in common organic solvents. The precursor polymer with structural units of formula (II) is thermally converted to the conjugated polymer with structural formula (III).

Abstract: A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises the steps of depositing and patterning a disposable layer, depositing a first barrier layer on top of the patterned disposable layer, depositing a metal layer, planarizing the metal layer, depositing a second barrier layer, planarizing the second barrier layer until substantially no barrier layer material is present on top of the disposable layer, depositing a permeable layer, removing the disposable layer through the permeable layer to form air gaps.

Abstract: A method for determining programming/erase conditions and a method for operating a charge-trapping semiconductor device are disclosed. Programming and erase conditions are determined such that a first net charge distribution variation profile, upon going from programmed to erased state, is substantially the opposite of a second net charge distribution variation profile, upon going from erased to programmed state.

Abstract: A method and apparatus for designing an ESD protection circuit comprising a main ESD device and a triggering device connected to a triggering node of the main ESD device by means of which the main ESD device can be triggered for conducting ESD current at a reduced voltage. The triggering device is located in an initial current path for the ESD current. In this initial current path, there is at least one triggering component which can be triggered from an off-state to an on-state. The triggering speed of this component is considered and its design is optimised in view of increasing its triggering speed. Further shown is an ESD protection circuit in which at least one triggering component is selected to be of a predetermined type for achieving a fast triggering speed, preferably of the gated diode type.

Abstract: Low work function metals for use as gate electrode in nMOS devices are provided. The low work function metals include alloys of lanthanide(s), metal and semiconductor. In particular, an alloy of nickel-ytterbium (NiYb) is used to fully silicide (FUSI) a silicon gate. The resulting nickel-ytterbium-silicon gate electrode has a work function of about 4.22 eV.