Abstract: A current sense resistor integrated with an integrated circuit die where the integrated circuit die is housed in a flip-chip semiconductor package includes a metal layer formed over a passivation layer of the integrated circuit die where the metal layer having an array of metal pillars extending therefrom. The metal pillars are electrically connected to a first leadframe portion and a second leadframe portion of the semiconductor package where the first leadframe portion and the second leadframe portion are electrically isolated from each other and physically separated by a separation of a first distance. The current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second leadframe portions, the first and second leadframe portions forming terminals of the current sense resistor.

Abstract: A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.

Abstract: A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.

Abstract: A voltage regulator includes a power device formed by an NMOS transistor having a drain terminal coupled to an input voltage, a source terminal providing an output voltage and a gate terminal receiving a gate drive signal; and an integrated AC/DC control loop configured to access the output voltage and to generate the gate drive signal based on a value of the output voltage in relation to a first reference voltage and a second reference voltage. The AC control portion generates a gate drive control signal which is AC coupled to the gate terminal of the power device as an AC component of the gate drive signal. The DC control portion controls a DC voltage level of the gate drive signal. The AC control portion is powered by the input voltage while the DC control portion is powered by a high supply voltage greater than the input voltage.

Abstract: A switching regulator using current mode control and adaptive slope compensation includes a DC correction circuit to introduce a DC correction signal to cancel the DC offset error generated by the slope compensation signal. In some embodiments, the DC correction signal is a function of the input voltage and the output voltage and is applied in response to the slope compensation signal being applied. In one embodiment, the DC correction signal is a linear function of the input voltage and the output voltage.

Abstract: A buck switching regulator implements a fixed frequency feedback control circuit including a voltage control loop and a frequency control loop to regulate the switching frequency of the buck switching regulator to a fixed or nearly fixed frequency. The voltage control loop, implementing ripple mode control, is configured to control the power switches in response to the switching regulator output voltage or a signal related to the switching regulator output voltage. The frequency control loop, implementing a phase-locked loop control scheme, is configured to adjust the on-time of the high-side switch so as to regulate the switching frequency to be equal to or be proportional to the reference frequency.

Abstract: A buck switching regulator includes a feedback control circuit using a four-input comparator to regulate the output voltage to a substantially constant level with reduced voltage offset and with fast transient response. In some embodiments, the buck switching regulator uses the four-input comparator to compare a first feedback signal without ripple and a second feedback signal with injected ripple components to a reference level. The four-input comparator generates an output signal to control the switching of the power switches. The buck switching regulator generates an output voltage with increased accuracy and fast transient response. Furthermore, the buck switching regulator can be used with output capacitor having any value of ESR.

Abstract: A hold-up circuit coupled to a first node to receive an input voltage and to provide a hold-up voltage includes an inductor, a constant on-time buck-boost control circuit configured to drive a high-side power switch and a low-side power switch to operate in a buck mode and a boost mode of operation, and an energy storage capacitor. When the input voltage is greater than a predetermined threshold, the buck-boost control circuit is configured to drive the power switches in the boost mode to charge the capacitor to a capacitor voltage greater than the input voltage. When the input voltage is less than the predetermined threshold, the buck-boost control circuit is configured to drive the power switches in the buck mode to supply the energy stored on the capacitor to the inductor to provide a regulated voltage less than the capacitor voltage as the hold-up voltage to the first node.

Abstract: A boost switching regulator incorporates a peak inductor current modulation circuit to modulate the peak inductor current as a function of the load current, the input voltage, the regulated output voltage, and a fixed current value. In this manner, the switching frequency of the boost regulator can be maintained above a given value or within a given frequency range over a wide range of load conditions and also over input voltage variations and output voltage settings.

Abstract: A boost switching regulator incorporates a ripple injection circuit to generate a voltage ripple signal for feedback control that mimics the actual ripple signal of the regulated output voltage. In this manner, the ripple injection circuit achieves optimal ripple injection for stable and enhanced feedback control. In one embodiment, the injected ripple signal is generated from a current injection signal that mimics the difference between the inductor current that flows through the synchronous rectifier and the load current when the synchronous rectifier is on. The injected voltage ripple signal is generated when the current injection signal is integrated by a feedforward capacitor.

Abstract: A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit implements a binary jump method and an operating curve is selected when the operating curve has an output frequency meeting the target frequency with the control voltage being within a first voltage range being a narrowed and centered voltage range within the control voltage range.

Abstract: A power system for providing an output current at a regulated system output voltage includes a first power stage and a second power stage, each being a constant on-time (COT) controlled power converter. The first and second power stages generate respective first and second regulated output voltage having reduced or very small output ripple at a common output voltage node. The first and second power stages each includes a ripple injection circuit to inject a ripple signal to the feedback control circuit in each power stage. The power system further includes a current sharing control circuit configured to measure a first output current of the first power stage and a second output current of the second power stage, and to generate a control signal to modulate the feedback control circuit of the second power stage to force the second output current to equal to the first output current.

Abstract: A buck switching regulator includes a feedback control circuit including a first gain circuit generating a first feedback signal indicative of the regulated output voltage; a ripple generation circuit generating a ripple signal that is injected to the first feedback signal; and a comparator receiving a first reference signal and the first feedback signal to generate a comparator output signal. The switching regulator further includes an offset compensation circuit including a second gain circuit generating a second feedback signal indicative of the regulated output voltage; and an operational transconductance amplifier (OTA) configured to receive the second feedback signal and the first reference signal and to generate an output signal. The output signal of the OTA is coupled to the comparator to adjust an offset to the comparator so as to cancel the offset at the regulated output voltage due to the injected ripple signal.

Abstract: A time-to-digital converter (TDC) incorporates a resistor-stabilized delay line, a sampling circuit and a processing circuit. The resistor-stabilized delay line operates to limit the variation in delay values for the delay elements in the delay line due to fabrication process variations. In some embodiments, the resistor-stabilized delay line limits the delay variation of each delay element to a fraction of the delay.

Abstract: A planar vertical DMOS transistor uses a conductive spacer structure formed on the sides of a dielectric structure as the gate of the transistor. The planar vertical DMOS transistor with a conductive spacer gate structure reduces the parasitic gate-to-bulk or gate-to-drain overlap capacitance by eliminating the conductive gate material that is formed above the bulk of the semiconductor layer. Meanwhile, the desired distance between the body regions formed on opposing sides of the conductive spacer gate structure is maintained.

Abstract: A planar vertical DMOS transistor includes a dielectric separation structure formed under the conductive gate and over the bulk of the semiconductor layer outside of the channel region of the transistor. The planar vertical DMOS transistor with a conductive gate formed over the dielectric structure reduces the parasitic gate-to-bulk or gate-to-drain overlap capacitance by increasing the separation between the conductive gate and the bulk of the semiconductor layer. Meanwhile, the desired distance between the body regions formed on opposing sides of the conductive gate is maintained.

Abstract: A signal level detect circuit configured to assess an input signal with varying amplitude signal levels and to generate an indicator signal includes an input circuit configured to receive the input signal and to process the input signal, the input circuit including a first node on which the input signal is sampled; a comparator configured to compare the processed input signal to a signal level threshold and generate a comparator output signal; and an active discharge circuit configured to provide a first discharge current to the first node in response to the comparator output signal. The comparator output signal changes from a low output state to a high output state in response to the comparator input signal, and the active discharge circuit generates the first discharge current to discharge the sampled input signal on the first node after the comparator output signal changes to the high output state.

Abstract: A battery charger voltage control method dynamically adjusts the system voltage generated by a battery charger circuit based on the operating conditions to ensure that sufficient power is supplied to power up the circuitry of the electronic device when the battery charger circuit is connected to a current-limited power source and the battery of the electronic device is deeply depleted or is missing. In embodiments of the present invention, the battery charger voltage control method sets the system voltage to an elevated voltage value to maximize the energy transfer from the power source to the circuitry of the electronic device. In this manner, the battery charger voltage control method enables a near instant boot-up of the electronic device, even under the operating conditions where the battery of the electronic device is deeply depleted or missing and the switching battery charger circuit can only receive power from a current-limited power source.

Abstract: A buck switching regulator implements a fixed frequency feedback control circuit including a voltage control loop and a frequency control loop to regulate the switching frequency of the buck switching regulator to a fixed or nearly fixed frequency. The voltage control loop, implementing ripple mode control, is configured to control the power switches in response to the switching regulator output voltage or a signal related to the switching regulator output voltage. The frequency control loop, implementing a phase-locked loop control scheme, is configured to adjust the on-time of the high-side switch so as to regulate the switching frequency to be equal to or be proportional to the reference frequency.

Abstract: A buck switching regulator includes a feedback control circuit using a four-input comparator to regulate the output voltage to a substantially constant level with reduced voltage offset and with fast transient response. In some embodiments, the buck switching regulator uses the four-input comparator to compare a first feedback signal without ripple and a second feedback signal with injected ripple components to a reference level. The four-input comparator generates an output signal to control the switching of the power switches. The buck switching regulator generates an output voltage with increased accuracy and fast transient response. Furthermore, the buck switching regulator can be used with output capacitor having any value of ESR.