Abstract: A buck switching regulator includes a feedback control circuit including a first gain circuit configured to generate a first feedback signal indicative of the regulated output voltage; a ripple generation circuit configured to generate a ripple signal using the switching output voltage and to inject the ripple signal to the first feedback signal; a second gain circuit configured to generate a second feedback signal indicative of the regulated output voltage; an operational transconductance amplifier (OTA) configured to generate an output signal having a magnitude indicative the difference between the second feedback signal and the first reference signal; and a comparator configured to generate a comparator output signal having an output level indicative of the difference between the output signal of the OTA and the first feedback signal. As thus configured, the buck switching regulator generates an output voltage with increased accuracy and fast transient response.

Abstract: A method for forming identical isotropic etch patterns in an etch system is disclosed. The method comprises providing a wafer paddle, a wafer, a plurality of identical etch systems, utilizing identical etch recipes within each of the plurality of etch systems, providing a fixed temperature stability time FTST for each system so that the heat transfer from the paddle to the wafer is constant, wherein the FTST is the same on each of the plurality of etch systems; and utilizing the plurality of identical etch systems to produce identical etches on each of the wafers based upon the FTST, wherein a five-second preheat step in the etch process is not utilized.

Abstract: A noise discriminator circuit and a noise discrimination method in a burst mode receiver is configured to determine the validity of an incoming burst signal by analyzing the timing of the signal edges of incoming signal to look for a time duration conforming to the preamble data bits of a valid burst signal. In one embodiment, the noise discriminator circuit and method analyze the time duration between signal edges of the same pulse of an incoming signal. In another embodiment, the noise discriminator circuit and method analyze the time duration between a first set of pulses of an incoming signal and the time duration between signal edges of a second set of pulses of the incoming signal. When the time durations are within a given time range relating to a predetermined timing separation of a valid burst signal, the incoming signal is validated as a valid burst signal.

Abstract: A noise discriminator circuit and a noise discrimination method in a burst mode receiver is configured to determine the validity of an incoming burst signal by analyzing the timing of the signal edges of incoming signal to look for a time duration conforming to the preamble data bits of a valid burst signal. In one embodiment, the noise discriminator circuit and method analyze the time duration between signal edges of the same pulse of an incoming signal. In another embodiment, the noise discriminator circuit and method analyze the time duration between a first set of pulses of an incoming signal and the time duration between signal edges of a second set of pulses of the incoming signal. When the time durations are within a given time range relating to a predetermined timing separation of a valid burst signal, the incoming signal is validated as a valid burst signal.

Abstract: A method for stitching a first field mask to a second field mask on a wafer includes providing a photomask with a first set of targets and a second set of targets, printing images of the first set of targets and the second set of targets onto the wafer where the photomask is applied to the wafer having no previous alignment marks formed thereon for the photomask to align to. A first set of alignment marks is formed from the first set of targets and a second set of alignment marks is formed from the second set of targets. The method includes aligning a first field mask to the first set of alignment marks and aligning a second field mask to the second set of alignment marks. The images of the first field mask and the second field mask are thereby stitched together on the wafer.

Abstract: A multi-modulus divider includes a chain of n dual modulus divider cells in cascade and connected in a ripple configuration where the last (n-k) of the divider cells are state-parked dual modulus divider cells. The state-parked dual modulus divider cells are forced to a given logical state when the divider cell is bypassed. The state-parked dual modulus divider cells ensure that the multi-modulus divider can change between different number of cells without clock glitches or clock errors. The multi-modulus divider is therefore capable of achieving a wide division range with seamless transition between division ratios.

Abstract: A multi-mode pulse width modulation (PWM) controller for a buck switching regulator includes a multi-mode PWM control circuit where the PWM control circuit is configured to operate in one of multiple control schemes selectable by a mode select signal. In one embodiment, the multi-mode PWM control circuit incorporates a peak current mode control scheme, a voltage mode control scheme, and a valley current mode control scheme. In another embodiment, the multi-mode PWM control circuit further incorporates a constant ON-time control scheme.

Abstract: A hold-up circuit coupled to a first node to receive an input voltage and to provide a hold-up voltage includes an inductor, a constant on-time buck-boost control circuit configured to drive a high-side power switch and a low-side power switch to operate in a buck mode and a boost mode of operation, and an energy storage capacitor. When the input voltage is greater than a predetermined threshold, the buck-boost control circuit is configured in the boost mode to drive the low-side power switch with constant on-time pulses and to charge the energy storage capacitor under non-synchronous operation. When the input voltage is less than a predetermined threshold, the buck-boost control circuit is configured in the buck mode to drive the high-side power switch with constant on-time pulses and to drive the low-side power switch under synchronous operation to provide the hold-up voltage to the first node.

Abstract: A method to form a LDMOS transistor includes forming a gate/source/body opening and a drain opening in a field oxide on a substrate structure, forming a gate oxide in the gate/source/body opening, and forming a polysilicon layer over the substrate structure. The polysilicon layer is anisotropically etched to form polysilicon spacer gates separated by a space in the gate/source/body opening and a polysilicon drain contact in the drain opening. A body region is formed self-aligned about outer edges of the polysilicon spacer gates, a source region is formed self-aligned about inner edges of the polysilicon spacer gates, and a drain region is formed under the polysilicon drain contact and self-aligned with respect to the polysilicon spacer gates. A drift region forms in the substrate structure between the body region and the drain region, and a channel region forms in the body region between the source region and the drift region.

Abstract: A battery charger voltage control method dynamically adjusts the system voltage generated by a battery charger circuit based on the operating conditions to ensure that sufficient power is supplied to power up the circuitry of the electronic device when the battery charger circuit is connected to a current-limited power source and the battery of the electronic device is deeply depleted or is missing. In embodiments of the present invention, the battery charger voltage control method sets the system voltage to an elevated voltage value to maximize the energy transfer from the power source to the circuitry of the electronic device. In this manner, the battery charger voltage control method enables a near instant boot-up of the electronic device, even under the operating conditions where the battery of the electronic device is deeply depleted or missing and the switching battery charger circuit can only receive power from a current-limited power source.

Abstract: A method for stitching a first field mask to a second field mask on a wafer includes providing a photomask with a first set of targets and a second set of targets, printing images of the first set of targets and the second set of targets onto the wafer where the photomask is applied to the wafer having no previous alignment marks formed thereon for the photomask to align to. A first set of alignment marks is formed from the first set of targets and a second set of alignment marks is formed from the second set of targets. The method includes aligning a first field mask to the first set of alignment marks and aligning a second field mask to the second set of alignment marks. The images of the first field mask and the second field mask are thereby stitched together on the wafer.

Abstract: A current sense resistor integrated with an integrated circuit die where the integrated circuit die is housed in a chip-scale semiconductor package includes a metal layer formed over a passivation layer of the integrated circuit die where the metal layer has an array of metal pillars extending therefrom. The metal pillars are to be electrically connected to a first conductive trace portion and a second conductive trace portion formed on a printed circuit board where the first conductive trace portion and the second conductive trace portion are electrically isolated from each other and physically separated by a separation of a first distance. The current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second metal trace portions, the first and second conductive trace portions forming terminals of the current sense resistor.

Abstract: A network device includes a physical layer transceiver configured to receive incoming data on a data link at an input clock rate and to store the incoming data in a buffer. The physical layer transceiver includes a Media Independent Interface (MII) controller configured to receive the incoming data stored in the buffer and to transmit the incoming data over a MII bus based on a MII clock where the MII clock is a spread spectrum clock. The network device further includes a Media Access Control (MAC) device configured to receiving incoming data from the physical layer transceiver over the MII bus where the incoming data is clocked by the spread spectrum MII clock.

Abstract: The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on a p-type substrate, and an asymmetric conductive spacer which acts as its gate. The LDMOS transistor also includes a source and a drain region on either side of the asymmetric conductive spacer, and a channel region formed by ion-implantation on the asymmetric conductive spacer. The height of the asymmetric conductive spacer increases from the source region to the drain region. The channel region is essentially completely under the asymmetric conductive spacer and has smaller length than that of the channel region of the prior art LDMOS transistors. The LDMOS transistor of the present invention also includes a field oxide layer surrounding the active region of the transistor, and a thin dielectric layer isolating the asymmetric conductive spacer from the n-type epitaxial layer.

Abstract: A driver circuit for controlling a high-side power switch of a switching regulator includes: a logic circuit configured to generate a gate control signal for turning on the power switch; a diode having coupled to a first power supply voltage; a capacitor having a first electrode coupled to the cathode of the diode and a second electrode coupled to the switching output voltage; and a delay circuit configured to receive the gate control signal and to generate a delayed gate control signal. In operation, the capacitor is precharged to about the first power supply voltage. When the power switch is turned on, a first output drive transistor is turned on to distribute the charge stored on the capacitor to the gate terminal of the high-side power switch, and after the predetermined delay, a second output drive transistor is turned on to drive the output node to a high supply voltage.

Abstract: A step-down hysteretic current LED driver circuit implements frequency regulation to adjust the hysteresis levels of a hysteretic comparator in the control circuit of the LED driver to keep the switching frequency of the inductor current constant. More specifically, the switching frequency of the inductor current is kept constant by increasing or decreasing the hysteresis window of the hysteretic comparator. In this manner, the switching frequency of the LED driver is kept constant or predictable. In one embodiment, the control circuit of the LED driver includes a frequency regulator to monitor the switching frequency and adjusts the hysteresis window accordingly to maintain a constant switching frequency.

Abstract: A voltage regulator includes a power device formed by an NMOS transistor having a drain terminal coupled to an input voltage, a source terminal providing an output voltage and a gate terminal receiving a gate drive signal; and an integrated AC/DC control loop configured to access the output voltage and to generate the gate drive signal based on a value of the output voltage in relation to a first reference voltage and a second reference voltage. The AC control portion generates a gate drive control signal which is AC coupled to the gate terminal of the power device as an AC component of the gate drive signal. The DC control portion controls a DC voltage level of the gate drive signal. The AC control portion is powered by the input voltage while the DC control portion is powered by a high supply voltage greater than the input voltage.

Abstract: A device for Electro-Magnetic Interference (EMI) reduction in an Ethernet system has an Ethernet compatible device. The Ethernet compatible device has a filter for adjusting a signal outputted by the Ethernet compatible device for EMI reduction.

Abstract: A method to form a LDMOS transistor includes forming a gate/source/body opening and a drain opening in a field oxide on a substrate structure, forming a gate oxide in the gate/source/body opening, and forming a polysilicon layer over the substrate structure. The polysilicon layer is anisotropically etched to form polysilicon spacer gates separated by a space in the gate/source/body opening and a polysilicon drain contact in the drain opening. A body region is formed self-aligned about outer edges of the polysilicon spacer gates, a source region is formed self-aligned about inner edges of the polysilicon spacer gates, and a drain region is formed under the polysilicon drain contact and self-aligned with respect to the polysilicon spacer gates. A drift region forms in the substrate structure between the body region and the drain region, and a channel region forms in the body region between the source region and the drift region.

Abstract: A step-down hysteretic current LED driver circuit implements frequency regulation to adjust the hysteresis levels of a hysteretic comparator in the control circuit of the LED driver to keep the switching frequency of the inductor current constant. More specifically, the switching frequency of the inductor current is kept constant by increasing or decreasing the hysteresis window of the hysteretic comparator. In this manner, the switching frequency of the LED driver is kept constant or predictable. In one embodiment, the control circuit of the LED driver includes a frequency regulator to monitor the switching frequency and adjusts the hysteresis window accordingly to maintain a constant switching frequency.