Abstract: Electrostatic discharge protection for integrated circuits, particularly for enhancing electrostatic discharge protection performance for Input-output cells and power supply clamps used in CMOS and BiCMOS IC technologies is described. A P-type, implantation region, or layer, referred to as “P-deep,” in both N-MOSFET and P-MOSFET devices is provided to enhance electrostatic discharge protection performance. Parasitic transistor gain is enhanced by providing the P-deep region subposing the drain contact. Exemplary embodiments for N-type and P-type MOSFETs, MOSFETs with surface diodes, MOSFETS with SCRs, and push-pull Input-output CMOS circuits are described.

Abstract: A field effect transistor (FET) driver circuit includes an error amplifier for providing a FET control signal and a current limiting amplifier for preventing excessive current flow through the FET. The current limiting amplifier generates an overcurrent signal when an excessive current is detected. In response to the overcurrent signal, a voltage control circuit adjusts the voltage at the output of the error amplifier to turn off the FET. Meanwhile, a pulldown circuit at an input of the error amplifier adjusts the voltage provided to that input to cause the error amplifier to provide an output voltage that also tends to turn off the FET. If a buffer is present at that input to the error amplifier, a second pulldown circuit is placed at the input to the buffer to maintain a stable unity gain across the buffer.

Abstract: In master-slave current-tracking load-share systems using switching power supplies, a method and apparatus for preventing current recirculation at light-load and no-load operational conditions. The slave power supply is run in a discontinuous mode when load current falls to light-load or no-load state, preventing the slave from sinking current, therefore preventing recirculation from the master to the slave. The slave power supply is run at a lower current level than the master, preventing recirculation from the slave to the master.

Abstract: Describe is a device for a multiplexing, output current-sensed, boost converter circuit which may be used as an LED driver. A boost converter LED driver circuit using a single set of passive external LC components for controlling the current through, and thus the output of, one and more than one bank of LEDs. The present invention allows for regulated current in one and more than one bank of LEDs by sensing current in the controller. The output voltage of a switcher adjusts it's level automatically until the current to the LEDs is set to the desired LED threshold requirement.

Abstract: A BiCMOS auxiliary output driver is provided to maintain output logic signal levels when integrated circuit chip power supply voltage is outside its nominal range. When the power supply voltage level is within design tolerance for a MOSFET output driver stage, the auxiliary output driver is off; when below design tolerance, the auxiliary output driver is turned on. Driver stage output pad signal level is maintained at a desired state level by the auxiliary output driver whenever the power supply slips below its design tolerance range.

Abstract: A common-mode feedback circuit is provided for fully-differential operational amplifier stages of a multistage amplifier. A first stage of the circuit establishes a substantially constant current output level for a feedback generating stage of the circuit. An exemplary embodiment using MOSFET devices illustrates using a diode-connected MOSFET and mirror MOSFET first stage and a generating the current for a common-source connected MOSFET second stage connected to the respective outputs for said fully-differential operational amplifier. An output stage of the circuit provides feedback voltage at a first level when inputs to said fully-differential operational amplifier are in equilibrium and at a second level for balancing said fully-differential operational amplifier when inputs to said fully-differential operational amplifier are not in equilibrium.

Abstract: A differential CMOS amplifier includes two CMOS inverters and biasing circuitry providing feedback loops across the output and input of each inverter. The biasing circuitry provides linear biasing so that the inverters can apply a desired gain to a pair of high frequency input signals (i.e., a differential input signal). The biasing circuitry can include operational amplifiers (op-amps) for providing positive feedback control between the output and input of the inverters. The inputs of the inverters can be regulated by this feedback loop such that their outputs are driven to the reference voltage, thereby forcing the inverters to operate in their linear regions so that non-distorting amplification can be applied to the input AC signals.

Abstract: A CMOS amplifier includes a CMOS inverter and a bias circuit coupled in a feedback loop between the output and input of the inverter. The bias circuit provides linear biasing so that the inverter can apply a desired gain to a high frequency input signal. The bias circuit can include an operational amplifier (op-amp) providing positive feedback control between the output and input of the inverter. By providing a reference voltage to the other input of the op-amp, the input of the inverter is regulated such that its output is driven to the reference voltage. This in turn forces the inverter to operate in its linear region, so that the inverter applies non-distorting amplification to the input AC signal. The AC signal is prevented from affecting the operation of the bias circuit by resistors coupling the bias circuit to the op-amp.

Abstract: The present invention provides an apparatus and method for improving the accuracy of circuits. The apparatus includes a replicate circuit and a trim determination circuit. The trim determination circuit includes a measurable circuit element and determines the state of the measurable element. The replicate circuit includes a replicate circuit element which has similar electrical characteristics as the measurable element, and is configured to aid in determining an adjustable test current. The trim determination circuit generates a test current which is proportional to the adjustable test current. The test current is passed through the measurable element such that a first voltage drop occurs across the measurable element. A measured current is generated at a current level dictated by the voltage drop across the measurable element, such that the state of the measurable element is determined by the difference between the measured current and a scaled reference current.

Abstract: A differential CMOS amplifier includes two CMOS inverters and biasing circuitry providing feedback loops across the output and input of each inverter. The biasing circuitry provides linear biasing so that the inverters can apply a desired gain to a pair of high frequency input signals (i.e., a differential input signal). The biasing circuitry can include operational amplifiers (op-amps) for providing positive feedback control between the output and input of the inverters. The inputs of the inverters can be regulated by this feedback loop such that their outputs are driven to the reference voltage, thereby forcing the inverters to operate in their linear regions so that non-distorting amplification can be applied to the input AC signals.

Abstract: Systems and methods for the measurement of optical power in optical fiber are disclosed. The optical signal is converted to an electrical signal, which is then converted to a digital output code that indicates the relative strength of the optical signal in terms of logarithmic units.

Abstract: IGBTs and circuits can be designed to improve the ability of circuits and systems to withstand ESD events. In addition pads can be designed to take advantage of the circuits and IGBTs to withstand and dissipate ESD events.

Abstract: A BiCMOS auxiliary output driver is provided to maintain output logic signal levels when integrated circuit chip power supply voltage is outside its nominal range. When the power supply voltage level is within design tolerance for a MOSFET output driver stage, the auxiliary output driver is off; when below design tolerance, the auxiliary output driver is turned on. Driver stage output pad signal level is maintained at a desired state level by the auxiliary output driver whenever the power supply slips below its design tolerance range.

Abstract: Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described.

Abstract: Embodiments of a bipolar transistor are disclosed, along with methods for making the transistor. An exemplary transistor includes a collector region in a semiconductor substrate, a base layer overlying the collector region and bound by a field oxide layer, a dielectric isolation layer overlying the base layer, and an emitter structure overlying the dielectric isolation layer and contacting the base layer through a central aperture in the dielectric layer. The transistor may be a heterojunction bipolar transistor with the base layer formed of a selectively grown silicon germanium alloy. A dielectric spacer may be formed adjacent the emitter structure and over a portion of the base layer.

Abstract: An electrostatic discharge (ESD) protection circuit that includes an transistor with a gate electrode isolated from the semiconductor substrate. The transistor can be an insulated gate bipolar transistor (IGBT) connected between an integrated circuit (IC) pad and ground. The IGBT includes a parasitic thyristor that latches when the voltage at the pad exceeds a threshold level and does not turn off until the charge at the pad is dissipated, thereby preventing electrostatic damage to the IC.

Abstract: A method and structure are provided that reduce the overall time of the read-erase-modify-write cycle time of non-volatile memories. Specifically, the erase operation of the read-erase-write cycle is avoided in certain circumstances. In one embodiment, the erase operation is skipped where a predetermined pattern is found in at least a portion the block. In another embodiment, the erase operation is skipped where a status of the block indicates that the erase operation can be skipped.

Abstract: The present invention provides an apparatus and method for improving the accuracy of circuits. The apparatus includes a replicate circuit and a trim determination circuit. The trim determination circuit includes a measurable circuit element and determines the state of the measurable element. The replicate circuit includes a replicate circuit element which has similar electrical characteristics as the measurable element, and is configured to aid in determining an adjustable test current. The trim determination circuit generates a test current which is proportional to the adjustable test current. The test current is passed through the measurable element such that a first voltage drop occurs across the measurable element. A measured current is generated at a current level dictated by the voltage drop across the measurable element, such that the state of the measurable element is determined by the difference between the measured current and a scaled reference current.

Abstract: An electrostatic discharge (ESD) protection circuit which includes an Insulated Gate Bipolar Transistor (IGBT), a collector clamp, and a resistor. The IGBT collector is coupled with a circuit pad, and the emitter is coupled to ground. The collector clamp is coupled with the pad and the IGBT gate, and the resistor is coupled with the IGBT emitter and gate. When the voltage at the pad is below the trigger voltage of collector clamp, the collector clamp remains in a blocking state, thus preventing the IGBT from conducting. At the onset of an ESD event, when a voltage greater than the trigger voltage of the collector clamp appears at the pad, the collector clamp conducts, causing current flow through the resistor, thus turning on the IGBT and latching a parasitic thyristor formed in the IGBT until the ESD charge is dissipated.

Abstract: A differential charge pump includes common mode circuitry for supplying a common mode voltage to a charging capacitor in the charge pump. The gate voltage of a reference transistor in a biasing branch of the differential charge pump is adjusted until the drain voltage of the reference transistor is equal to the common mode voltage when a specified bias current is flowing through the biasing branch. The same gate voltage and bias current are provided to a first transistor in a first common mode branch and a second transistor in a second common mode branch. The drains of the first transistor and the second transistor are connected to a first plate and a second plate, respectively, of the charging capacitor. In this manner, a desired common mode voltage is supplied to the charging capacitor.