Abstract: A BiCMOS integrated circuit (IC) includes a floating gate-type non-volatile memory (NVM) device that uses the polycrystalline silicon gate of a CMOS FET and the P-base and N-emitter diffusions of a bipolar transistor to provide an isolated P-type body and N-type source/drain diffusions. The P-body diffusion of the NVM device is isolated from a P-substrate by an N-well, thus facilitating the use of reduced positive and negative voltage levels to produce the onset of Fowler-Nordheim tunneling without the need for a triple-well structure. The polysilicon gate structure is formed on a suitable gate oxide over the P-body. The source/drain diffusions, which like the N-emitter diffusions of the bipolar transistor have no LDD, produce a reduced field drop across the gate oxide to allow Fowler-Nordheim tunneling from the source side.

Abstract: A Light-Emitting Diode (LED) driver circuit is disclosed that controls the brightness of light generated by a LED that is coupled between a first terminal and a second terminal in response to a user supplied brightness control signal. A constant current source generates a constant current that is supplied to the LED and to a shunt circuit, which his connected in parallel with the LED. A brightness control circuit generates a pulse signal having a duty cycle that is proportional to the brightness control signal, and controls the shunt circuit such that, when said pulse signal is high, the constant current is passed through the shunt circuit and the LED is turned off, and when the pulse signal is low, the constant current is passed through the LED. The duty cycle of the brightness control signal is adjusted to adjust the LED's brightness, while the LED color remains constant.

Abstract: An automatic power control system provides a control signal that regulates the output power of at least one laser diode. Coarse adjustment of the control signal is provided by a first means, preferably a digital variable resistor, while fine adjustment and compensation is provided by a second means, preferably by a digital-to-analog converter that receives an input signal proportional to a sensed control system parameter. The control system includes an operational amplifier having a first input coupled to sense output power, and a second input coupled to a DAC to provide finer resolution control. Memory can store system parameter or system parameter variations that can be coupled to the DAC and/or variable resistor to enhance system stability over ambient variations.

Abstract: A monitoring system comprising a plurality of devices, each including a shift register and a status register. The plurality of shift registers are coupled in a serial chain. The monitoring engine is configured to receive status information from the shift registers and monitor status of the connected devices. The monitoring engine has the capability to monitor fault and persistence counts for analog and digital artifacts. A method for monitoring a plurality of devices coupled in a serial chain is provided.

Abstract: A pin-limited device includes a pattern-recognition circuit that detects a predetermined signal pattern transmitted on a supply pin of the device. The predetermined signal pattern is generated within the acceptable operating voltage range of the IC device (e.g., between the minimum and maximum acceptable system voltage levels utilized to control the internal circuitry of the device). Accordingly, the pin-limited IC device continues to operate within specifications while the predetermined signal pattern is transmitted on the selected power supply pin or pins. A test mode circuit generates a switch control signal in response to the predetermined signal pattern to connect an output pin of the device, for example, to an internal node of the device. The pattern recognition circuit sets a latch when the predetermined signal pattern is detected, and the latch is reset when the device is powered down then powered up.

Abstract: An LDO regulator includes two linear regulator circuits and an internal priority logic scheme that favors generating a regulated output voltage using a regulated supply voltage over an unregulated supply voltage. The unregulated supply voltage is applied to a first input terminal from a raw voltage source. The regulated supply voltage is applied to a second input terminal from, for example, a switching (e.g., BUCK) regulator. Two output devices are respectively connected between the first and second input terminals and the LDO output terminal. The first regulator circuit causes the first output device to supply the desired regulated output voltage while the switching regulator ramps up. Once the regulated supply voltage is high enough to allow regulation, the internal priority logic scheme disables the first regulator circuit, whereby the desired regulated output voltage is generated solely by the second regulator circuit through the second output device.

Abstract: An analog soft-start circuit for a switching regulator (e.g., a buck converter) including an analog ramp circuit and an open-loop analog voltage clamp circuit. The voltage ramp circuit utilizes a two-stage current divider circuit to generate a very low, stable current signal, and an integrator circuit including a relatively small, integral capacitor to generate the ramp voltage signal in response to the very low current signal. The analog voltage clamp circuit clamps the regulated output signal to the ramp voltage until the ramp voltage signal increases to a predetermined voltage level, thereby causing the regulated output voltage to exhibit the desired soft-start characteristics. The analog clamp circuit includes a current mirror circuit that generates a clamp current that pulls down the error amplifier output stage via a clamping element (e.g., a diode) until the ramp voltage signal reaches a predetermined level.

Abstract: A bandgap reference circuit utilizes differential transistors to generate a temperature-independent bandgap voltage. In place of conventional trim elements that are connected in parallel to and adjust the resistance values of the bandgap reference circuit, current control circuits are placed in the current paths passing through the differential transistors (i.e., connected to the critical nodes located at the terminals of the differential transistors). Each current control circuit includes a resistive “trim” element (e.g., a zener diode) and associated trim pads that are separated from the critical nodes (i.e., the terminals of the differential transistors) by isolation transistors such that, during a trim/test procedure, the stray capacitances introduced by trim/test equipment probes are prevented from altering the performance of the bandgap reference circuit. In one embodiment, a current control circuit is connected to the critical node connected to the base of at least one of the differential transistors.

Abstract: A method of reducing the settling time of an amplifier includes providing a pre-set voltage on a high gain node of the amplifier when the amplifier is disabled. This pre-set voltage can be slightly less than the regulated voltage. In this manner, when the amplifier is enabled, the high gain node can quickly reach this regulated voltage. The pre-set voltage can be applied to the high gain node by operating a switch, e.g. if the amplifier is enabled (disabled), then the switch is open (closed). A startup circuit can generate the pre-set voltage. This startup circuit can include a startup current source and a transistor connected in series between VDD and VSS. The switch can be connected to the gate and drain of the transistor. Notably, the transistor can be the same type of device as the MOS device driven by the high gain node in the amplifier.

Abstract: An OTA driving an MOS device needs to turn it off quickly to minimize overshoot during a heavy to light load state. The drains of the MOS device can be used to accelerate turning off the MOS device. A first drain is connected to the gate of the MOS device. A second drain is connected to a base of a bipolar device. The emitter of the bipolar device is connected to the MOS device gate. Notably, this bipolar device is active during the heavy to light load state. Therefore, any current provided by the second drain is then multiplied by the beta of the bipolar device. The increased current generated on the emitter of the bipolar transistor and provided to the gate of the MOS device can advantageously accelerate the turnoff of that MOS device. The first drain can provide minimal additional current during the heavy to light load state.

Abstract: A delay-locked loop (DLL) circuit with mutual-interpolating architecture that provides multiple-phase clock generation is presented. Each delay-cell in the DLL circuit delay chain is effectively an interpolator that combines two input clock signals: one input clock signal is received from the output clock of previous stage in the delay chain, and the other input clock signal is fed back from a following stage. Each delay cell supports the concurrent functions of delay and interpolation. The architecture imposes a set of N simultaneous equations, where N is the total number of delay clock signals, to control the clock waveforms. These simultaneous equations obtain a unique solution when the DLL enters a lock state, and the generated delay clock signals inherently have a clock duty cycle of 50%. The delay chain can be implemented using either odd or even number of delay cells.

Abstract: A delay-locked loop (DLL) employs an in-loop duty cycle corrector (DCC) to provide accurate multiphase clock generation with 50% duty cycle. Each delay cell can advantageously provide both delay and duty cycle correction functionality. In one embodiment, delay correction can precede duty cycle correction. The bandwidths of the DCC and the DLL can differ by a factor of a decade to achieve fast and stable operation.

Abstract: Control loops in a voltage regulator can be stabilized using minimal silicon area. A current limit signal, generated by a current limit control loop in the voltage regulator, can be divided to minimize a zero provided in a compensation set associated with a voltage control loop, thereby stabilizing both loops. The compensation set can include a resistor (the zero) and a capacitor (a pole) connected in series between output and input terminals of an amplifier. Dividing the current limit signal can include injecting a first portion of the current limit signal on a first side of the resistor and injecting a second portion of the current limit signal on a second side of the resistor. The ratio of the first and second portions can be based on a gain of the amplifier, thereby minimizing an effect of the resistor.

Abstract: A delay-locked loop (DLL) circuit with mutual-interpolating architecture that provides multiple-phase clock generation is presented. Each delay-cell in the DLL circuit delay chain is effectively an interpolator that combines two input clock signals: one input clock signal is received from the output clock of previous stage in the delay chain, and the other input clock signal is fed back from a following stage. Each delay cell supports the concurrent functions of delay and interpolation. The architecture imposes a set of N simultaneous equations, where N is the total number of delay clock signals, to control the clock waveforms. These simultaneous equations obtain a unique solution when the DLL enters a lock state, and the generated delay clock signals inherently have a clock duty cycle of 50%. The delay chain can be implemented using either odd or even number of delay cells.

Abstract: A thermal shutdown system that can accurately detect a chip overheat condition or a local overheat condition is described. This system can include a first shutdown circuit triggered by the chip overheat condition and a second shutdown circuit triggered by the local overheat condition. The second shutdown circuit can be located near the heat-generating component on the IC. The first shutdown circuit can be located in another area of the IC. A common temperature independent signal, which indicates whether a local overheat condition is anticipated, can enable one shutdown circuit and disable the other shutdown circuit. An enabled shutdown circuit can respond to a temperature sensitive signal to indicate a fault condition, i.e. Ea chip/local overheat condition.

Abstract: A single chip superhetrodyne AM receiver is disclosed herein. To compensate for process variations in the implementation of the IC, bias currents setting the operating conditions for various amplifiers and other components in the system are adjusted based on frequency control signals in a PLL circuit in the local oscillator. Since the magnitude of the control signal reflects the process variations, the bias currents are adjusted based on the control signal to offset these variations in other portions of the receiver. To further improve the signal to noise ratio of the receiver, the IF filter is tuned within a range so as not to include any integer multiple or integer divisor of the timing reference frequency. Various techniques are described for enabling a complete superhetrodyne AM receiver to be implemented on a single chip which receives an antenna input signal and outputs a digital data signal.

Abstract: An improved method of canceling a RHPZ of a switching regulator can include detecting a predetermined error signal provided to a pulse width modulation (PWM) circuit, wherein the predetermined error signal is associated with the RHPZ. Once a RHPZ is detected, a ramp waveform provided to the PWM circuit can be temporarily lengthened, thereby canceling the RHPZ. Notably, temporarily lengthening the ramp waveform can be based on adjusting an RZ*CZ time constant. In one embodiment, the ramp waveform can be lengthened to create a left half-plane zero (LHPZ), which improves stability.

Abstract: A timer circuit includes a current mirror, a capacitor, a first switch, a resistor and a comparator. The current mirror receives a reference current and provides first and second currents with a predefined current ratio. The capacitor receives the first current as a sinking current or as a sourcing current. The first switch, controlled by a control signal, allows the capacitor to be charged by the first current or be discharged. The resistor is biased by the second current to provide an adaptive reference voltage. The comparator compares the voltage across the capacitor and the adaptive reference voltage and triggers an output signal when the capacitor voltage is increased to the adaptive reference voltage.

Abstract: An improved method of canceling a RHPZ of a switching regulator can include detecting a predetermined error signal provided to a pulse width modulation (PWM) circuit, wherein the predetermined error signal is associated with the RHPZ. Once a RHPZ is detected, a ramp waveform provided to the PWM circuit can be temporarily lengthened, thereby canceling the RHPZ. Notably, temporarily lengthening the ramp waveform can be based on adjusting an RZ*CZ time constant. In one embodiment, the ramp waveform can be lengthened to create a left half-plane zero (LHPZ), which improves stability.

Abstract: A pin-limited device includes a pattern-recognition circuit that detects a predetermined signal pattern transmitted on a supply pin of the device. The predetermined signal pattern is generated within the acceptable operating voltage range of the IC device (e.g., between the minimum and maximum acceptable system voltage levels utilized to control the internal circuitry of the device). Accordingly, the pin-limited IC device continues to operate within specifications while the predetermined signal pattern is transmitted on the selected power supply pin or pins. A test mode circuit generates a switch control signal in response to the predetermined signal pattern to connect an output pin of the device, for example, to an internal node of the device. The pattern recognition circuit sets a latch when the predetermined signal pattern is detected, and the latch is reset when the device is powered down then powered up.