Abstract: A voltage regulator output stage can include a power device whose body to source junction is forward biased using a MOSFET trigger. The forward biasing can advantageously reduce the threshold voltage of the power device, thereby effectively increasing its gate drive as well as its output current capability. Controlling the forward biasing using the MOSFET trigger provides minimal leakage, thereby ensuring that the output stage is commercially viable as well as performance enhanced.

Abstract: A voltage regulator including a bandgap control circuit that maintains the regulator's bandgap voltage at a predetermined voltage level after an externally generated enable signal is de-asserted until the regulated output voltage has dropped below a predetermined low reference voltage. The bandgap control circuit includes a latch that is set by the enable control signal to generate a bandgap control signal, which is used to activate a bandgap reference generator that generates the bandgap voltage. The latch is reset to de-assert the bandgap control signal by a logic gate and a low output voltage detector. The detector generates a low output voltage detection signal when the regulated output voltage falls below a low reference voltage. The logic gate generates a rising edge signal that resets the latch only when the enable signal is de-asserted and the detector generates the detection signal, thereby preventing unintended shutdown of the bandgap reference generator.

Abstract: A thermal shutdown system that can accurately detect a chip overheat condition or a local overheat condition is described. This system can include a first shutdown circuit triggered by the chip overheat condition and a second shutdown circuit triggered by the local overheat condition. The second shutdown circuit can be located near the heat-generating component on the IC. The first shutdown circuit can be located in another area of the IC. A common temperature independent signal, which indicates whether a local overheat condition is anticipated, can enable one shutdown circuit and disable the other shutdown circuit. An enabled shutdown circuit can respond to a temperature sensitive signal to indicate a fault condition, i.e. a chip/local overheat condition.

Abstract: A low-dropout voltage (LDO) regulator that creates a zero in the open loop gain using a relatively small-sized current control element to divert part of the supplied load current through a “zero” resistor before adding it to the output load. The main part of the output load is passed through a relatively large second current control element, and both the current control elements are controlled by a control signal generated by an error amplifier (e.g., an op-amp). The voltage signal developed across the “zero” resistor mimics the magnitude and phase of a zero in the loop. This voltage signal is added to the loop gain by, for instance, using a bypass capacitor, and the resulting feedback signal is supplied to the error amplifier, which generates a control signal by comparing the feedback signal with a stable reference voltage.

Abstract: In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.

Abstract: A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable structure includes a third region and a fourth region of opposite conductivity types. The first region of the diode and the third region of the programmable structure are electrically connected. In operation, the programmable structure is programmed to a low impedance state when a voltage exceeding a first breakdown voltage of the programmable structure is applied to reverse bias the programmable structure. The programmable element can be used to form a programmable array having very low parasitic capacitance, enabling the realization of a large and ultra fast programmable logic array.

Abstract: A timer circuit includes a current mirror, a capacitor, a first switch, a resistor and a comparator. The current mirror receives a reference current and provides first and second currents with a predefined current ratio. The first switch, controlled by a control signal, allows the capacitor to be charged by the first current or be discharged. The resistor is biased by the second current to provide an adaptive reference voltage. The comparator compares the voltage across the capacitor and the adaptive reference voltage and triggers an output signal when the capacitor voltage is increased to the adaptive reference voltage. Alternately, the timer circuit includes a pin for coupling to an external resistor and an open pin detector circuit to detect the presence of the external resistor and to automatically select the adaptive reference voltage if a resistor is present or an internal reference voltage if the resistor is absent.

Abstract: A comparator circuit having improved operational characteristics. A predetermined voltage drop device is provided, such as an exemplary embodiment Schottky diode, having an anode connected to circuit power supply voltage and an output stage of the comparator and a cathode connected to an input stage of the comparator. The predetermined voltage drop device effects a lowering of the power supply voltage for the output stage bias between said power supply voltage and said common voltage. This reduces the required swing of the output stage drivers during a comparator input signal transition and reduces propagation delay of said comparator.

Abstract: A circuit and method for programming and control of an integrated circuit includes a control pin receiving an applied input voltage selected from a set of predetermined programming voltages and an on-chip control voltage decode circuit to select one of multiple programming states for the integrated circuit based on the applied input voltage. In one embodiment, an off-chip voltage divider is used to establish the set of predetermined programming voltages. The on-chip control voltage decode circuit includes a voltage divider to generate comparison voltage levels for detecting the voltage level of the input voltage for selecting the desired programming state. The comparison voltage levels include voltages having voltage values that are midway between pairs of adjacent programming voltages. The voltage decode circuit includes a control circuit receiving comparison results from comparators and generating an output control signal for selecting the desired digital state based on the comparison results.

Abstract: A non-synchronous boost converter includes a switched Schottky diode to rectify the switched output voltage of the boost converter where the switched Schottky diode has forward conduction blocking capability. The switched Schottky diode has an anode terminal coupled to receive the switched output voltage, a cathode terminal providing the output DC voltage, and a gate terminal coupled to receive a control signal. The control signal has a first state for turning the switched Schottky diode on where the switched Schottky diode conducts current when forward biased and a second state for turning the switched Schottky diode off where forward conduction of the switched Schottky diode is blocked even when the diode is forward biased. The switched Schottky diode can be a JFET controlled or an LDMOS gate controlled Schottky diode. Furthermore, the switched Schottky diode can be formed on-chip or off-chip of the controller circuit of the boost converter.

Abstract: A transistor is formed with a source ballast resistor that regulates channel current. In an LDMOS transistor embodiment, the source ballast resistance may be formed using a high sheet resistance diffusion self aligned to the polysilicon gate, and/or by extending a depletion implant from under the polysilicon gate toward the source region. The teachings herein may be used to form effective ballast resistors for source and/or drain regions, and may be used in many types of transistors, including lateral and vertical transistors operating in a depletion or an enhancement mode, and BJT devices.

Abstract: A current sense resistor circuit using Kelvin connection sense features provides an average voltage across net sense resistance and average voltage across net reference resistance to be available at the Kelvin connection points. The Kelvin connections can be used by a negative feedback gain loop to hold the average current through respective reference elements and sense elements substantially constant.

Abstract: A field effect transistor (FET) driver circuit includes an error amplifier for providing a FET control signal and a current limiting amplifier for preventing excessive current flow through the FET. The current limiting amplifier generates an overcurrent signal when an excessive current is detected. In response to the overcurrent signal, a voltage control circuit adjusts the voltage at the output of the error amplifier to turn off the FET. Meanwhile, a pulldown circuit at an input of the error amplifier adjusts the voltage provided to that input to cause the error amplifier to provide an output voltage that also tends to turn off the FET. If a buffer is present at that input to the error amplifier, a second pulldown circuit is placed at the input to the buffer to maintain a stable unity gain across the buffer.

Abstract: An incremental or bit by bit address decode scheme allows each device on a serial bus to determine as soon as possible if it is the device being addressed by a master device. As each address bit is received serially into a device, it is immediately compared with a corresponding bit of the device's address. As soon as there is a bit not matching, the device in question is determined to not be the one addressed by the master device. It can then be disengaged from the communication process and free up as soon as possible its internal resource initially reserved for possible access by the master device.

Abstract: A current mirror includes a serially connected diode-connected transistor of a first conductivity type, a saturated (fully-on) transistor of a second conductivity type, and a current source for providing a reference current. A gate voltage generated by the diode-connected transistor in response to the reference current is provided to the gate of a matching transistor. This causes the matching transistor to mirror the reference current. Meanwhile, an output transistor cascoded with the matching transistor is gate-coupled to the junction between the saturated transistor and the current source. This allows the output transistor to provide an output voltage swing from one supply voltage to two saturation voltage drops from the second supply voltage. Meanwhile, the cascode configuration gives the current mirror a high output impedance.

Abstract: A common-mode feedback circuit is provided for fully-differential operational amplifier stages of a multistage amplifier. A first stage of the circuit establishes a substantially constant current output level for a feedback generating stage of the circuit. An exemplary embodiment using MOSFET devices illustrates using a diode-connected MOSFET and mirror MOSFET first stage and a generating the current for a common-source connected MOSFET second stage connected to the respective outputs for said fully-differential operational amplifier. An output stage of the circuit provides feedback voltage at a first level when inputs to said fully-differential operational amplifier are in equilibrium and at a second level for balancing said fully-differential operational amplifier when inputs to said fully-differential operational amplifier are not in equilibrium.

Abstract: In master-slave current-tracking load-share systems using switching power supplies, a method and apparatus for preventing current recirculation at light-load and no-load operational conditions. The slave power supply is run in a discontinuous mode when load current falls to light-load or no-load state, preventing the slave from sinking current, therefore preventing recirculation from the master to the slave. The slave power supply is run at a lower current level than the master, preventing recirculation from the slave to the master.

Abstract: A surge current delay time period is added to a current limit delay time period in order to permit a longer time for a possibly temporary larger-than-steady-state electrical current, such as for a start-up power requirement. A system is described for permitting a legitimate surge current by distinguishing true over-current fault conditions from temporary surges in terms of high current duration time.

Abstract: In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.

Abstract: A current sense resistor circuit using Kelvin connection sense features provides an average voltage across net sense resistance and average voltage across net reference resistance to be available at the Kelvin connection points. The Kelvin connections can be used by a negative feedback gain loop to hold the average current through respective reference elements and sense elements substantially constant.