Abstract: A level shifter circuit includes two parallel current paths respectively controlled by switch transistors, a Wilson current mirror circuit, and a slew rate control circuit to selectively couple an output node either to a high (first) voltage source or to a ground (second voltage) source in response to differential input control signals signal. When the output node reaches a stable (high or low) voltage level, the low voltage on one of the current paths turns off a Wilson current mirror transistor in the other current path, thereby preventing quiescent current during stable periods. An optional cascode transistor is added to facilitate fabrication using low threshold voltage transistors.

Abstract: A Dual Input, Single Output Low Dropout Regulator (LDO) includes two linear regulator circuits and control circuitry that produce an overlap period during change-over between a regulated supply voltage and an unregulated supply voltage wherein both supply voltages are coupled to the LDO output pin. The unregulated supply voltage is supplied, e.g., by a battery, and the regulated supply voltage is supplied from a switching-type DC-DC converter. First and second output devices are connected between the LDO output terminal and the unregulated and regulated supply voltages, respectively. The first regulator circuit causes the first output device to supply the desired regulated output voltage while the switching regulator ramps up. The regulator circuits then turn on the second output device and gradually turn off the output device, whereby the regulated output voltage transitions from the unregulated supply voltage to the regulated supply voltage is achieved without severe voltage transients.

Abstract: A level shifter circuit includes two parallel current paths respectively controlled by switch transistors, a Wilson current mirror circuit, and a slew rate control circuit to selectively couple an output node either to a high (first) voltage source or to a ground (second voltage) source in response to differential input control signals signal. When the output node reaches a stable (high or low) voltage level, the low voltage on one of the current paths turns off a Wilson current mirror transistor in the other current path, thereby preventing quiescent current during stable periods. An optional cascode transistor is added to facilitate fabrication using low threshold voltage transistors.

Abstract: A low-dropout voltage (LDO) regulator that creates a zero in the open loop gain using a relatively small-sized current control element to divert part of the supplied load current through a “zero” resistor before adding it to the output load. The main part of the output load is passed through a relatively large second current control element. A control signal generated by an error amplifier (e.g., an op-amp) is used to control the small current control element, but is passed through a boost zero compensating resistor before being applied to the large current control element. The voltage signal developed across the “zero” resistor mimics the magnitude and phase of a zero in the loop. This voltage signal is added to the loop gain by, for instance, using a bypass capacitor, and the resulting feedback signal is supplied to the error amplifier.

Abstract: A single chip superhetrodyne AM receiver is disclosed herein. To compensate for process variations in the implementation of the IC, bias currents setting the operating conditions for various amplifiers and other components in the system are adjusted based on frequency control signals in a PLL circuit in the local oscillator. Since the magnitude of the control signal reflects the process variations, the bias currents are adjusted based on the control signal to offset these variations in other portions of the receiver. To further improve the signal to noise ratio of the receiver, the IF filter is tuned within a range so as not to include any integer multiple or integer divisor of the timing reference frequency. Various techniques are described for enabling a complete superhetrodyne AM receiver to be implemented on a single chip which receives an antenna input signal and outputs a digital data signal.

Abstract: A LED driver circuit avoids undesirable light generated by a LED due to leakage current by shunting the output terminal to the feedback terminal during periods when it is desired that the LED remain turned off. The shunting operation is achieved by providing a switch (e.g., a FET) that is connected between the output and feedback terminals of the LED, and is controlled by the user supplied reference signal. During active operation (i.e., when the user supplied reference signal is “enabled” and the LED is lit), the switch remains open, allowing the driver circuit to generate the desired driving voltage across the LED. During inactive periods (i.e., when the user supplied reference signal is “disabled” and the LED is intended to be off), the switch is closed, which couples the output and feedback terminals to generate an essentially zero voltage drop across the LED.

Abstract: Evaluating an embedded EPROM in a host IC device involves using program circuitry to program/unprogram all of the floating-gate cells of the embedded EPROM, then simultaneously transmitting a predetermined test bias voltage to all of the programmed/unprogrammed floating-gate cells, and then evaluating the output terminals of all of the floating-gate cells using a logic (e.g., wired NOR or NAND) circuit, whereby successful operation of all of the embedded EPROM cells causes the wired logic circuit to generate a single positive test result signal, and the failure of one or more of the embedded EPROM cells causes the wired logic circuit to generate a single negative test signal. A reference cell is also evaluated using a bias testing circuit to determine that the reference voltage supplied during normal operation is at an acceptable voltage level.

Abstract: Evaluating an embedded EPROM in a host IC device involves using program circuitry to program/unprogram all of the floating-gate cells of the embedded EPROM, then simultaneously transmitting a predetermined test bias voltage to all of the programmed/unprogrammed floating-gate cells, and then evaluating the output terminals of all of the floating-gate cells using a logic (e.g., wired NOR or NAND) circuit, whereby successful operation of all of the embedded EPROM cells causes the wired logic circuit to generate a single positive test result signal, and the failure of one or more of the embedded EPROM cells causes the wired logic circuit to generate a single negative test signal. A reference cell is also evaluated using a bias testing circuit to determine that the reference voltage supplied during normal operation is at an acceptable voltage level.

Abstract: A line driver includes current sources and resistors that form a bridge circuit in which a bridge resistor is connected between an internal node and ground, and a series resistor connected between the internal node and the driver's output node. The internal node is connected to receive a unit current from a first stage transistor, and the output node is connected to receive an amplified current from a second stage transistor that is N times the unit current. The bridge resistor is formed with a resistance value set such that the voltages at the internal node and the output node are equal, i.e., such that no current flows through the series resistor. The resistance value of the series resistor is thus adjustable to optimize output impedance in a manner independent of the driver's gain. An echo cancellation circuit is utilized to eliminate noise from two associated line drivers.

Abstract: Noise reducing circuitry may be included in a pulse width modulation circuit. The pulse width modulation circuit may include a comparator adapted to receive an analog signal and a sawtooth signal and to compare such signals to generate a pulse width output. In general, the noise reducing circuitry may include a sawtooth signal generating circuit configured to generate a sawtooth signal including an up ramp and a sawtooth signal including a down ramp. A control circuit may be coupled to the sawtooth signal generating circuit for controlling the sawtooth signal generating circuit based on whether a relatively narrow or relatively wide pulse width is to be output by the pulse width modulation circuit. Methods for reducing noise in a pulse width modulation circuit may generally involve dynamically controlling a direction of ramp of a sawtooth signal that is to be input to the comparator of the pulse width modulation circuit.

Abstract: An LED driver circuit may include dimming circuitry. In particular, the LED driver circuit may include a switching converter, an LED and a switch. The LED may be electrically connected to the switching converter and the switch may be connected in parallel with the LED. The switching converter and/or the switch may be configured to be controlled to achieve dimming of the LED. Current may be supplied to the LED and the switch may be turned on and off to dim the LED. The switching converter coupled to the LED may include a switching element in series with an inductor and the LED. In such case, the switching element may be turned on to supply current to the LED and the inductor, and the switch may be turned on and off to dim the LED.

Abstract: A dual-channel load switch circuit may be provided for switching between first and second sources that generate respective input voltages. The circuit may include first and second channels adapted to receive the respective input voltages and to supply respective output voltages to a load element based on the respective input voltages. The first and second channels may each include first and second switching elements and first and second control circuitry. The second channel may include a diode in parallel with the second switching element and may be coupled to the first control circuitry. The circuit may include a reservoir element coupled to the first and second channels and configured to store a potential when one of the first and second channels supplies a respective output voltage to the load element and to apply the potential to the load element when neither output voltage is being supplied to the load element.

Abstract: A slice level reference generator and method for performing improved data slicing operations when gaps are present in a data stream is disclosed that involves applying a nominal reference signal to the comparator the during signal gaps. In one embodiment, a receiver circuit includes a slice level detector and a comparator that operate in a conventional manner, and control circuitry that utilizes a signal detector and a switch to store a slice level reference signal generated by the slice level detector during a first signal burst, and to apply the stored reference signal to the comparator during signal gaps. In one embodiment a timer circuit is used to detect signal gaps. In another embodiment a predetermined fixed reference signal is applied to the comparator during signal gaps.

Abstract: A voltage regulator output stage can include a power device whose body to source junction is forward biased using a MOSFET trigger. The forward biasing can advantageously reduce the threshold voltage of the power device, thereby effectively increasing its gate drive as well as its output current capability. Controlling the forward biasing using the MOSFET trigger provides minimal leakage, thereby ensuring that the output stage is commercially viable as well as performance enhanced.

Abstract: A fast settling AGC system includes a “fast settle” comparator that facilitates fast settling of strong radio receiver output signals from a maximum to an intermediate voltage level at the start of each transmission burst, and a “normal” AGC comparator that further settles the output signal from the intermediate voltage level to a desired target output voltage level at a slower “normal” rate. The gain control signal components generated by both the “fast settle” comparator and the “normal” AGC comparator are summed and applied to the gain control terminal of a variable gain amplifier. The gain control signal component generated by the “fast settle” comparator has a higher current level than the gain control signal component generated by the “normal” comparator, but is terminated when receiver output signal drops to the intermediate voltage level.

Abstract: A LED driver circuit avoids undesirable light generated by a LED due to leakage current by shunting the output terminal to the feedback terminal during periods when it is desired that the LED remain turned off. The shunting operation is achieved by providing a switch (e.g., a FET) that is connected between the output and feedback terminals of the LED, and is controlled by the user supplied reference signal. During active operation (i.e., when the user supplied reference signal is “enabled” and the LED is lit), the switch remains open, allowing the driver circuit to generate the desired driving voltage across the LED. During inactive periods (i.e., when the user supplied reference signal is “disabled” and the LED is intended to be off), the switch is closed, which couples the output and feedback terminals to generate an essentially zero voltage drop across the LED.

Abstract: An LDO regulator includes two linear regulator circuits and an internal priority logic scheme that favors generating a regulated output voltage using a regulated supply voltage over an unregulated supply voltage. The unregulated supply voltage is applied to a first input terminal from a raw voltage source. The regulated supply voltage is applied to a second input terminal from, for example, a switching (e.g., BUCK) regulator. Two output devices are respectively connected between the first and second input terminals and the LDO output terminal. The first regulator circuit causes the first output device to supply the desired regulated output voltage while the switching regulator ramps up. Once the regulated supply voltage is high enough to allow regulation, the internal priority logic scheme disables the first regulator circuit, whereby the desired regulated output voltage is generated solely by the second regulator circuit through the second output device.

Abstract: In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.

Abstract: A portable device includes a voltage regulator for generating a regulated voltage that is supplied to a processor and to a load by way of a line protection switch, which controls a load current supplied to the load, e.g., in response to a signal supplied by the processor. The line protection switch includes a gate control circuit with a comparator that detects a short circuit in the load by comparing the regulated voltage against a reference voltage. When a short circuit causes the regulated voltage to drop below a predetermined minimum voltage (e.g., 4.5V), the comparator de-asserts the control signal, thereby turning off the switch before the regulated output voltage falls below a minimum operating voltage (e.g., 4.35V) of the processor.

Abstract: A bandgap reference circuit utilizes differential transistors to generate a temperature-independent bandgap voltage. In place of conventional trim elements that are connected in parallel to and adjust the resistance values of the bandgap reference circuit, current control circuits are placed in the current paths passing through the differential transistors (i.e., connected to the critical nodes located at the terminals of the differential transistors). Each current control circuit includes a resistive “trim” element (e.g., a zener diode) and associated trim pads that are separated from the critical nodes (i.e., the terminals of the differential transistors) by isolation transistors such that, during a trim/test procedure, the stray capacitances introduced by trim/test equipment probes are prevented from altering the performance of the bandgap reference circuit. In one embodiment, a current control circuit is connected to the critical node connected to the base of at least one of the differential transistors.