Abstract: A high force flip chip bonding method and system that precisely and forcefully engage a flip chip device with a corresponding wiring pattern on a substrate in a manner that prevents flip chip device and substrate shifting during force application. The method includes the steps of determining the centroid of the pattern formed by the interconnects on the flip chip device. The flip chip device is directed toward the substrate for contacting the corresponding wiring pattern with the interconnects and then the interconnects are compressed into the corresponding wiring pattern using a bonding force. The bonding force is directed along a neutral axis of deflection that is coincident with the centroid. Applying the bonding force along the neutral axis of deflection at the centroid minimizes lateral shifting of the flip chip device relative to the substrate to precisely bond the interconnects to the corresponding wiring pattern.

Abstract: A matrix-addressed diode flat panel display of field emission type is described, utilizing a diode (two terminal) pixel structure. The flat panel display includes a cathode assembly having a plurality of cathodes, each cathode including a layer of cathode conductive material and a layer of a low effective work-function material deposited over the cathode conductive material and an anode assembly having a plurality of anodes, each anode including a layer of anode conductive material and a layer of cathodoluminescent material deposited over the anode conductive material, the anode assembly located proximate the cathode assembly to thereby receive charged particle emissions from the cathode assembly, the cathodoluminescent material emitting light in response to the charged particle emissions.

Abstract: A customizable circuit using a programmable interconnect and compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form long diagonal lines having a pitch determined by the basic wire segment length. Uniform capacitance effects are achieved by alternating the layers of the wire segments. The terminal ends of the segments are positioned in a plane such that segments may be connected by short links to form the desired interconnect. The links which join the line segments customize the otherwise undedicated interconnect. Resistive links may be used to minimize undesirable transmission line effects. The segment ends may also be connected through electrically programmable elements. Carrier tape bonds the integrated circuit chips to the programmable interconnect.

Abstract: A hybrid superconducting-semiconducting field effect transistor-like circuit element comprised of a superconducting field effect transistor and a closely associated cryogenic semiconductor inverter for providing signal gain is described. The hybrid circuit functions nearly as an ideal pass gate in cryogenic cross-bar applications.

Abstract: Apparatus for converting superconductor low level signals to semiconductor signal levels utilizing a continuous superconductor to semiconductor converter circuit biased for maximum gain and without the need for a clocked reset signal. Employing a unique biasing arrangement utilizing two capacitors and one transistor, this circuit has long term bias voltage retention and good power supply noise rejection ratio.

Abstract: A process for manufacturing a pin grid array package providing a plurality of electrical input and/or output connections using a plurality of stacked, but spaced apart, separate leadframes which are preformed and include a plurality of electrical leads having first and second ends for providing a plurality of different connections. An insulating layer is positioned between adjacent leadframes and the package is bonded together.

Abstract: A method of making sub-micron low work function field emission tips without using photolithography. The method includes physical vapor deposition of randomly located discrete nuclei to form a discontinuous etch mask. In one embodiment an etch is applied to low work function material covered by randomly located nuclei to form emission tips in the low work function material. In another embodiment an etch is applied to base material covered by randomly located nuclei to form tips in the base material which are then coated with low work function material to form emission tips. Diamond is the preferred low work function material.

Abstract: An improved method for inhibiting tin whisker growth involving the implantation in a tin coating of an ion or ions selected from the group Pb, Bi, Sb, Tl, Cu, Ag, Au, Cd, Mo, Cr, W, Ar, He, Ne and Kr.

Abstract: Direct fabrication of three-dimensional metal parts by irradiating a thin layer of a mixture of metal powder and temperature equalization and unification vehicle to melt the metal powder and form a solid metal film. The vehicle also protects the molten metal from oxidation. The metal powder can contain an elemental metal or several metals, the vehicle can be an organic resin or an amalgam, and the irradiation can be selectively applied by a YAG laser.

Abstract: A three dimensional integrated circuit interconnect for connecting a plurality of chips in a module with a standard footprint for pin grid array or quad flat pack mounting. Each IC is mounted on a custom interconnect slice and tested. The slices are stacked together with electrical connections from one slice layer to the next. The module may use multi-layer ceramic slices or printed circuit board materials.

Abstract: A method of forming an etch mask and patterning a substrate. The method includes directing a particle beam at a substrate without using a mask to deposit an etch mask on the substrate which selectively exposes predetermined portions of the substrate, the etch mask consisting of particles mechanically placed on the substrate by the particle beam, and then etching the exposed portions of the substrate through the etch mask to form channels therein. The process is well suited to fabricating high density copper/polyimide multi-chip modules.

Abstract: A maskless process for forming a protected metal feature in a planar insulating layer of a substrate is disclosed. A first barrier material is disposed in a recess in an insulating layer, a conductive metal is disposed on the first barrier material such that the entire metal feature is positioned within the recess below the top of the recess, a second barrier material is disposed on the metal feature such that the second barrier material occupies the entire portion of the recess above the metal feature and extends above the top surface of the insulating layer, and the second barrier material is then polished until the top of the second barrier material is in and aligned with the top of the insulating layer. As a result, the metal feature is surrounded and protected by the first and second barrier materials, and the substrate is planarized.

Abstract: An peripheral to area adapter for an integrated circuit chip. The adapter comprises pads on an upper surface of a support in a pattern corresponding to the terminals on a integrated circuit, planar reroute lines on the upper surface with first ends at the pads, and vertical conductive vias extending through the support. The vias are connected at the upper surface to the second ends of the reroute lines. The vias are connected at the lower surface of the support to an area array of coupling elements. The pads and reroute lines can be fabricated on a tape-automated-bonding (TAB) frame support and personalized to match a particular configuration of terminals or bumps on a chip. The coupling elements can form a generic array compatible with a wide variety of interconnect substrates.

Abstract: A high force flip chip bonding method and system that precisely and forcefully engage a flip chip device with a corresponding wiring pattern on a substrate in a manner that prevents flip chip device and substrate shifting during force application. The method includes the steps of determining the centroid of the pattern formed by the interconnects on the flip chip device. The flip chip device is directed toward the substrate for contacting the corresponding wiring pattern with the interconnects and then the interconnects are compressed into the corresponding wiring pattern using a bonding force. The bonding force is directed along a neutral axis of deflection that is coincident with the centroid. Applying the bonding force along the neutral axis of deflection at the centroid minimizes lateral shifting of the flip chip device relative to the substrate to precisely bond the interconnects to the corresponding wiring pattern.

Abstract: A coaxial bump for connecting a die to a substrate includes a center post and a ground ring surrounding and shielding the center post. The center post may be a center conductor line, and the ground ring may be generally torus-shaped, nearly closed or completely closed. The coaxial bump provides very low crosstalk in chip-to-substrate interconnections and provides a constant impedance with negligible inductive discontinuity.

Abstract: A process for making thermosetting or thermoplastic encapsulated integrated circuit having a heat exchanger in which one end of the heat exchanger is encapsulated in the housing adjacent to the integrated circuit and the other end is exposed to the environment beyond the housing portion. The process of making includes molding a heat exchanger into a thermosetting or thermoplastic package utilizing a preformed heat exchanger having a dissolvable or removable material which serves as a seal block during the molding operation. A plurality of thermally conductive heat exchanger elements are provided for providing the desired thermal performance while reducing the thermal stresses in the package.

Abstract: A field emitter comprising a conductive metal and a diamond emission tip with negative electron affinity in ohmic contact with and protruding above the metal. The field emitter is fabricated by coating a substrate with an insulating diamond film having negative electron affinity and a top surface with spikes and valleys, depositing a conductive metal on the diamond film, and applying an etch to expose the spikes without exposing the valleys, thereby forming diamond emission tips which protrude a height above the conductive metal less than the mean free path of electrons in the diamond film.

Abstract: An attribute-enhanced scroll bar is graphically displayed. A selected portion of a stored data file, for example a document, is displayed in a display field, and a scroll bar field including a scroll bar is used to indicate the position of the displayed portion relative to the entire data file. In addition, maps of significant task-specific attributes of the data file, for example particular character strings within a document, are displayed in the scroll bar field of the display along with the scroll bar. The attribute maps indicate the location of the significant attributes within the data file. In addition, the attributes are highlighted within the portion of the data file that is displayed in the display field.

Abstract: A method and apparatus for dispensing a thin coating of a highly viscous encapsulant liquid on to the top surface of a semiconductor device having been inner lead bonded. The coating is dispensed with a controlled thickness and is substantially planar. A liquid encapsulant having optimum thermal, chemical and mechanical properties is selected for protecting the electrical device and which is suitably controlled in an automated liquid dispensed process. The process is directed to various parameters which are required for achieving the desired quality, reliability, and automatic processing capability.

Abstract: A method for determining sequential hardware equivalence between two designs and whether one design can replace another design is disclosed whereby the designs are compared utilizing OBDD representations of the designs. The set of states in each of the designs that are equivalent to each other, equivalent-state-pairs, is first determined and it is then determined whether there exists a sequence of inputs that can take all states pairs to the equivalent-state-pair set. This results in a declaration of equivalence in the two designs. An essential reset sequence is then determined, which is then represented by the sequence of inputs to move the designs to a reset state. This, therefore, gives an essential reset sequence for the design and also gives the essential reset states for the design. The essential reset states of the design can then be compared to all states of the designs and, if they are equal, the design is replaceable.