Abstract: A thermally and electrically conductive paste for making a detachable and compliant connection between two surfaces. The paste comprises an equilibrium mixture of an electrically conductive liquid metal and particulate solid constituents, wherein at the temperature of the paste during connection the proportions of liquid metal and particulate solid constituents remain between the ultimate liquidus and the ultimate solidus of the phase diagram of the mixture and the paste remains non-solidified. in cryogenic and low temperature environments the paste forms a hardened bond with a TCE matched to a contacted surface.

Abstract: A testing and burn in socket compatible with the high density test pads located at small pitches devices on a TAB tape. A TAB tape carrier for supporting the TAB tape and a test circuit board having contact pads for electrical communication with the test pads. An alignment fixture positioned between the tape carrier and circuit board and including an opening in alignment between the test pads and the contact pads. A metal in elastomer matrix is positioned in the opening for providing electrical communication between the test pads and the contact pads. A block may be positoned in the openings and contain a plurality of straight parallel electrically conductive pins aligned with the matrix for high frequency tests.

Abstract: A method for electrolessly plating an overcoat metal on a metal conductor disposed on a dielectric surface of a substrate. The method includes removing carbonized film from the dielectric surface by applying a plasma discharge, acid treating the metal conductor by dipping the substrate in a first acid solution in order to clean the surface of the metal conductor, activating the metal conductor to allow electroless plating thereon by dipping the substrate in a metal activator solution, deactivating the dielectric surface to prevent electroless plating thereon without deactivating the metal conductor by dipping the substrate in a second acid solution, and plating an overcoat metal on the metal conductor by dipping the substrate in an electroless plating solution so that the overcoat metal plates on and coats the metal conductor without plating on the dielectric surface.

Abstract: A customizable circuit using a programmable interconnect and a compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form along diagonal lines having a pitch determined by the basic wire segment length. The terminal ends of each of these segments are positioned in a plane such that the segments may be connected by short lengths to form the desired interconnect. The links which join the line segments represent the customization of the otherwise undedicated interconnect. The TAB chip bonding design uses a carrier tape to bond the integrated circuit chips to the programmable interconnect. Also disclosed are methods for forming the interconnect and the TAB chip bonding design.

Abstract: A diffusion barrier which reduces the diffusion of a copper feature into an oxygen containing polymer is provided by a copper metal alloy. The diffusion barrier is fabricated by coating a metal on a copper feature, heating the metal and copper feature to form an alloy of the copper feature and the metal, etching the non-alloyed metal which covers the alloy, and depositing an oxygen containing polymer on the alloy. Preferably the metal is aluminum and a copper aluminum alloy diffusion barrier is at least 300 angstroms thick and contains at least 8 percent aluminum on the surface in contact with the polymer.

Abstract: Two cascaded eight-bit maskable counters (62) and (64) provide a sixteen-bit output, for instance, to a digital-to-analog converter (10). Each of the counters (62) and (64) is a maskable counter that is operable to mask off a programmable number of the least significant bits therein. The next adjacent bit thereto comprises a virtual least significant bit. During the counting operation, the count is initiated at the virtual least significant bit such that the virtual least significant bit is clocked for each counting cycle. An initial value is first loaded into the counter (62) and (64) on a data bus (74). Thereafter, masked data is loaded into the counters (62) and (64) on the same data bus (74) to define the ones of the least significant bits that are masked off. In such a manner, the overall resolution of the counter can be varied without varying the clock rate to the counter.

Abstract: A method of making bonding bumps on the pads of an electrical chip including depositing a layer of metallic adhesion material over the surface, depositing metallic bumps on the metallic adhesion material over each of the pad areas using a focused liquid metal ion source, and chemically etching the layer of metallic adhesion material off the surface outside of the deposited bumps.

Abstract: A defective metallization layer is removed from the top of an electronic component such as an integrated circuit or a copper/polyimide substrate by polishing with a rotating pad and a slurry. Non-defective underlying metallization layers are preserved and a new metallization layer is fabricated to replace the defective layer.

Abstract: A method for fabricating metal pillars in an electronic component. The method includes providing a base with spaced vias in a top surface, depositing an electrically conductive metal into the vias and over the top surface of the base so that a metal layer with an uneven top surface forms over the base, and planarizing the metal by polishing. The polishing can remove the entire metal layer leaving metal pillars in and aligned with the base. Or the polishing can be completed before removing the metal layer and metal above the base between the vias can be etched to form metal pillars with uniform heights which extend above the base. The invention is well suited for fabricating high-density multilayer copper/polyimide electrical interconnects.

Abstract: An apparatus and method for cutting strip or reel form of TAB tape into individual sites ready for further processing. In addition, a lead plating buss may be removed at the same time. A universal and adjustable apparatus includes preferably two cutter assemblies positioned adjacent a replaceable tape adapter and a clamp foot is actuated prior to cutting, for holding the tape, and is also magnetically attracted toward the movable cutter blade.

Abstract: A plating rack for use in electroplating at least one substrate includes a rack body onto which the substrate may be placed; a metal ring connected to the rack body so as to surround a substrate placed on the rack body; and bistable, single-tipped cam assemblies for holding a placed substrate in place and for making electrical contact between the metal ring and the substrate.

Abstract: An article provides sealing of an electronic component connected to a mating fluid heat exchanger by providing a diaphragm with an opening shaped to fit about the heat exchanger, the opening forming a sealing lip. A clamping ring, which expands and contracts as a function of temperature is placed around the lip of the diaphragm and subject to a temperature to shrink the clamping ring against the lip and heat exchanger for sealing the diaphragm thereto. Preferably the clamping ring is a shape memory alloy metal. In addition, a compressible metal seal may be placed between the lip and the heat exchanger to increase the ability to seal.

Abstract: A customizable circuit using a programmable interconnect and a compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form along diagonal lines having a pitch determined by the basic wire segment length. The terminal ends of each of these segments are positioned in a plane such that the segments may be connected by short lengths to form the desired interconnect. The links which join the line segments represent the customization of the otherwise undedicated interconnect. The TAB chip bonding design uses a carrier tape to bond the intergrated circuit chips to the programmable interconnect. Also disclosed are methods for forming the interconnect and the TAB chip bonding design.

Abstract: Solder reflow on an electrical interconnect substrate between a plurality of electrical contacts. The method includes coating the contacts with tin/lead solder, depositing a wetting metal between the contacts, and heating the substrate to at least the melting point of the solder so that the solder melts, reflows across the wetting metal and connects or links the contacts. The entire surface of a customizable copper/polyimide substrate can be personalized by solder links and TAB leads from surface-mounted integrated circuits can simultaneously be soldered to the substrate.

Abstract: A method of testing electrical circuits on a substrate for detecting shorts and opens. A plurality of electrical networks in which each network has one or more nodes are tested by selectively electrically charging certain nodes and selectively testing other nodes for detecting shorts and opens between the nodes. The method of testing allows various levels of testing to be performed for detecting more and greater different kinds of possible defects.

Abstract: A process for fabricating integrated resistors in high density interconnect substrates for multi-chip modules. In addition, the resistor material can be connected selectively into an insulator for optionally allowing for the simultaneous fabrication of integrated resistors and capacitors in relatively few steps. The process is well suited for cooper/polyimide substrates.

Abstract: Method for making a multilayer electrical interconnect with stacked pillars between layers using a minimal number of conventional process steps. The method includes sputtering a chromium/copper/titanium trilayer on a dielectric base, depositing a patterned mask on the trilayer, etching the exposed trilayer, removing the mask, depositing a layer of polyimide over the unetched copper, forming a via in the polyimide above the copper, electrolessly plating nickel into the via, and polishing the interconnect to form a planar top surface.

Abstract: A neural network includes an input layer comprising a plurality of input units (24) interconnected to a hidden layer with a plurality of hidden units (26) disposed therein through an interconnection matrix (28). Each of the hidden units (26) is a single output that is connected to output units (32) in an output layer through an interconnection matrix (30). Each of the interconnections between one of the hidden units (26) to one of the output units (32) has a weight associated therewith. Each of the hidden units (26) has an activation in the i'th dimension and extending across all the other dimensions in a non-localized manner in accordance with the following equation: ##EQU1## that the network learns by the Back Propagation method to vary the output weights and the parameters of the activation function .mu..sub.hi and .sigma..sub.hi.

Abstract: A method of making a metal-on-elastomer pressure contact connector. The method includes embedding a plurality of parallel co-planar copper-beryllia wires comprising a plurality of coils in a silicone rubber elastomer with top and bottom surfaces, and removing metal from the tops and bottoms of the coils to form a pair of isolated wire filaments from each coil which extend from the top surface to the bottom surface of the elastomer. The filaments form arrays of electrical contacts above and below the elastomer exceeding 10,000 contacts per square inch.

Abstract: Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias.