Abstract: Ionized metal cluster beam deposition of metal bumps on substrates such as multi-chip modules and integrated circuit chips is enhanced. The present invention discloses wet etching techniques for removing unwanted metal deposited on the substrate around bumps, multiple sources for depositing alloyed (tin-lead) bumps with constant composition, and single or multiple sources for directing a cluster beam through an aperture to deposit metal on a substrate and directing an ion beam at the aperture to remove metal deposited therein.

Abstract: The present invention discloses a thermally and electrically conductive adhesive material comprising a hardened adhesive, and a non-solidified filler containing a liquid metal dispersed in separate spaced regions of the adhesive. The hardened adhesive provides a mechanical bond whereas the filler provides continuous thermal and electrical metal bridges, each bridge extending through the adhesive and contacting the bonded surfaces. The method includes (a) dispersing a filler containing a liquid metal into an unhardened adhesive, (b) contacting the unhardened adhesive and the filler in non-solidified state to the surfaces resulting in separate spaced regions of the non-solidified filler contacting both surfaces, and (c) hardening the adhesive.

Abstract: A scalable visualization system includes a plurality of scalable tiles (10) that each comprise a display portion (18) and a processing portion (20). Each of the display portions (18) define a portion of a physical display space. Each of the processing sections defines a processing node in the parallel processing system. The parallel processing system operating on a single node or a plurality of nodes. A message fabric (36) is provided to connect CPU nodes (34) and each of the tiles (10) together. The tiles (10) are scaled by interconnecting them to form the desired display space with each of the display elements (18). As each tile (10) is added to the overall display space, an additional CPU node (34) is also added, such that not only is the display space scaled up from a physical coordinant standpoint, but the processing power is also scaled up. In addition, each of the CPU nodes (34) is operable to update an associated display list (28) that defines the parameters of the display element (18 ).

Abstract: An improved cathode for a sputtering system includes a metal cylinder and strips of material bonded to the inside of the metal cylinder and/or material sprayed onto the inside of the metal cylinder. The strips may have various specified compositions and/or configurations and/or other characteristics which enhance the ability of the sputtering system to deposit films of high temperature superconductor material on substrates.

Abstract: Three-dimensional metal parts are fabricated by irradiating a thin layer of a mixture of metal powder and temperature equalization and unification vehicle to melt the metal powder and form a solid metal film. The vehicle also protects the molten metal from oxidation. The metal powder can contain an elemental metal or several metals, the vehicle can be an organic resin or an amalgam, and the irradiation can be selectively applied by a YAG laser.

Abstract: Method of making a field emitter device with submicron low work function emission tips without using photolithography. The method includes depositing in situ by evaporating or sputtering a discontinuous etch mask comprising randomly located discrete nuclei. In one embodiment an ion etch is applied to a low work function material covered by a discontinuous mask to form valleys in the low work function material with pyramid shaped emission tips therebetween. In another embodiment an ion etch is applied to an electrically conductive base material covered by a discontinuous mask to form valleys in the base material with pyramid shaped base tips therebetween. The base material is then coated with a low work function material to form emission tips thereon.

Abstract: An encapsulated integrated circuit package having an integrated circuit chip with a plurality of electrical leads connected thereto and at least one thermally conductive screen mesh positioned adjacent to the chip. A non-electrically conductive thermosetting or thermoplastic material forms a housing enclosing the chip and bonded to the screen mesh. Preferably one of the layers is exposed to the outside of the housing and the screen mesh is secured to a substrate supporting the chip.

Abstract: A porous substrate curtain coated with a single coating of a liquid dielectric that is cured into a well adhering film at least 15 microns thick with a uniformity of less than 5 microns. The substrate is cleaned to remove contaminants, heated to remove moisture, curtain coated with a single coating of a viscous heat curable liquid dielectric such as polyimide, and heated to cure the dielectric by increasing the temperature at most 15.degree. C. per minute to a predetermined cure temperature not exceeding 450.degree. C. The invention is well suited for fabricating a dielectric layer in a high density multichip module.

Abstract: Ionized metal cluster beam deposition of metal bumps on substrates such as multi-chip modules and integrated circuit chips is enhanced. The present invention discloses wet etching techniques for removing unwanted metal deposited on the substrate around bumps, and multiple sources for depositing alloyed (tin-lead) bumps with constant composition.

Abstract: An peripheral to area adapter for an integrated circuit chip. The adapter comprises pads on an upper surface of a support in a pattern corresponding to the terminals on a integrated circuit, planar reroute lines on the upper surface with first ends at the pads, and vertical conductive vias extending through the support. The vias are connected at the upper surface to the second ends of the reroute lines. The vias are connected at the lower surface of the support to an area array of coupling elements. A protective bumper attached to the sides of the package provides mechanical shielding for the chip. The pads and reroute lines can be fabricated on a tape-automated-bonding (TAB) frame support and personalized to match a particular configuration of terminals or bumps on a chip. The coupling elements can form a generic array compatible with a wide variety of interconnect substrates.

Abstract: A process for producing fine pitch surface features on a multilayer printed circuit boards such as copper-polyimide interconnects without requiring a thick copper plating foil. Initially, a thin first conductor (less than 1 micron) is vacuum deposited on a dielectric base and the dielectric base is disposed on a substrate. The substrate is then laminated and through-holes are formed therethrough. A plating seed is deposited in the through-holes and resist is patterned on the first conductor. A second conductor is deposited on the exposed portions of the first conductor and on the sidewalls, the resist is stripped and the portions or the first conductor beneath the resist are removed using a brief wet chemical etch to form spaced features without significant undercut. In the preferred embodiment, vacuum deposition occurs in a continuous roll sputtering system.

Abstract: The excise and lead form of TAB leads bonded to an integrated circuit chip. Leads extending beyond a sidewall are clamped between a first clamp and a form anvil at a first portion spaced from the chip. The leads are also clamped between an excise/form tool and a second clamp at a second portion spaced further from the chip than the first portion. An excise blade cuts the leads outside the second portion. Then the excise/form tool, second clamp and excise blade move downwards in a curved path toward the chip to form a first lead corner against the form anvil and a second lead corner against the excise/form tool without splaying or galling the leads.

Abstract: A method for selectively electroplating a metallic coating, such as solder, onto a plurality of small and closely spaced electrical contacts. The method includes sealingly enclosing the contacts in an electroplating cell having an anode, a cathode and a chamber, forming an electrical connection between the cathode and the contacts and electroplating the contacts.

Abstract: The invention relates to an electrical interconnect device with power and ground lines interwoven about signal line layers and capacitive vias between signal layers so as to make efficient use of otherwise undedicated area between signal lines and signal layers and to reduce or eliminate the need for separate power and ground layers while providing decoupling capacitance within the wiring structure.

Abstract: A first laser beam and a second laser beam with a longer wavelength than the first laser beam are directed at a first metal member in contact with a second metal member. At the ambient temperature the first member has high absorption of energy from the first laser beam but low absorption of energy from the second laser beam. As the first member absorbs energy from the first laser beam the temperature of the first member increases and the reflectivity of the first member decreases so that the first member has high absorption of energy from the second laser beam. The first member then absorbs energy from the second laser beam, the temperature of the first member further increases and at least one of the members melts. After discontinuing the laser beams a solid bond forms between the members.

Abstract: An integrated circuit structure and method of making in which the circuit has a plurality of metal heat exchanger elements spaced from each other with their first ends secured to the structure. The first ends may be adhesively secured to an integrated circuit chip or the underlying substrate, and the heat exchanger may be hermetically attached. The method uses a compliant removable support block for attaching the plurality of individual heat exchanger elements to integrated circuit structures having variations in their elevation.

Abstract: A process for fabricating integrated resistors in high density interconnect substrates for multi-chip modules. In addition, the resistor material can be converted selectively into an insulator for optionally allowing for the simultaneous fabrication of integrated resistors and capacitors in relatively few steps. The process is well suited for copper/polyimide substrates.

Abstract: Apparatus for selecting memory cells in a MOS memory array and reading data contained therein. Superconducting Josephson junction devices switch between a superconducting and voltage gap mode for rapid selection of an addressed memory cell row and column, and then read out of the selected memory cell data contained therein.

Abstract: A method of depositing micron-sized metal lines on a dielectric substrate, such as polyimide. The dielectric is covered with a thin metallic layer, of a first metal placed in a reaction cell containing a gas-phase molecular species containing a second metal, and exposed to a focused laser beam. A translation stage moves the dielectric relative to the beam to selectively deposit micron-sized second metal lines on the metallic layer. The metallic layer on the unirradiated portion of the substrate is subsequently etched away, leaving the lines adhered to the dielectric surface.