Abstract: A method of patterning metal on a substrate without photolithography. The steps include providing a dielectric substrate, forming a metal mask in a predetermined pattern on the substrate without using a mask by direct-write deposition using a particle beam such as a liquid metal cluster force to form the mask, dry etching the substrate to form a plurality of channels therein, depositing a conductive metal into the channels, and removing the mask. The top of the substrate can then be planarized by polishing, or alternatively the dielectric between the metal lines can be etched. The invention is well suited for fabricating copper/polyimide substrates.

Abstract: A method of forming recessed patterns in insulators is described. One embodiment of the invention is directed to ceramic green sheet fabrication by providing a sculptured plastic tape mold which includes a floor, a plurality of sidewalls adjacent to and extending above the floor and a plurality of protrusions on and extending above the floor, casting a ceramic slurry into the mold such that the slurry contacts the floor, the sidewalls and the protrusions, and drying the slurry so as to produce a ceramic green sheet with a recessed pattern that replicates the shapes of the protrusions. The ceramic green sheet may be removed from the mold and filled with a conductor before firing; alternatively, the ceramic green sheet can be fired before removing the mold to form a rigid ceramic substrate which is then filled with a conductor.

Abstract: A metal/polymeric dielectric substrate has metal conductors selectively disconnected by photoablating the polymeric dielectric with an excimer laser, etching the exposed metal using the polymeric dielectric as a mask, and coating an additional layer of polymeric dielectric. This eliminates the need for depositing and removing a separate photoablatable mask. Siloxane-modified-polyimide is a preferred photoablatable polymeric material and copper is a preferred metal.

Abstract: A superconducting wire which includes a base wire and at least a superconduction layer formed on the base wire. The superconduction layer may be formed by using a sputtering system for depositing a film of high temperature superconductor material on the base wire. The superconducting wire may further include an adhesion layer, a diffusion barrier layer and/or a protection layer. Several superconducting wires may be grouped together in a metal matrix to form a composite superconducting wire.

Abstract: A method for forming via holes in a multilayer structure in a single step. The invention includes disposing over a base a first layer comprising first metal lines beneath a first dielectric, disposing over the first layer a second layer comprising second metal lines beneath a second dielectric such that a portion of each first metal line is not beneath any second metal line, and forming via holes which extend through the second dielectric to the second metal lines and through the second dielectric and the first dielectric to the portions of the first metal lines. Thereafter conductive metal can be deposited in the via holes. The method is particularly well suited for fabricating copper/polymer substrates.

Abstract: An amalgam and a method of preparing an amalgam for bonding two articles together, which includes mixing a composition of a liquid metal and a metal powder to thoroughly wet the metal powder with the liquid metal, and thereafter mixing a composition with a pestle element for mechanically amalgamating the composition. Other additives may be provided such as ductile metals, additives containing oxides, ceramics, or other non-metallic compounds, and volatile constituents. The amalgamated composition can then wet surfaces to be bonded and harden at or near room temperature.

Abstract: A method and apparatus for selectively electroplating a metallic coating, such as solder, onto a plurality of small and closely spaced electrical contacts. The method includes sealingly enclosing the contacts in an electroplating cell having an anode, a cathode and a chamber, forming an electrical connection between the cathode and the contacts and electroplating the contacts.

Abstract: A multilayered electrical interconnect circuit whereby interconnect lines, placed in channel regions throughout a rerouting substrate, function to reroute densely packaged electrical components via geometrically uniform spot links placed upon only the surface layer within each channel region. The interconnect circuit has closely spaced parallel X-and Y-lines orthogonal to one another, each X- and Y-line placed within horizontal and vertical channel regions, respectively, such that electrical connections between closely spaced large-scale integrated circuits or discrete electrical components can be rerouted with a combination of one or more X- and/or Y-lines.

Abstract: Trenching techniques for forming a channel partially through and a via completely through the insulating layer of a substrate are disclosed. With additional steps the channel can form an electrically conductive line, an electrode of an integrated capacitor, or an optical waveguide.

Abstract: A customizable interconnect circuit wherein a universal substrate of minimum layers is completely customized by programmable conductive links placed only on the top layer of the substrate. The customizable circuit having high density of orthogonally placed X- and Y-conductors capable of interconnecting closely spaced large-scale integrated circuits or discrete electrical components. By utilizing a plurality of interconnect cells regularly spaced throughout a universal, fixed substrate, interconnect routing from overlying electrical components or integrated circuits can be more directly routed to target areas.

Abstract: Removing welded outer lead bonds of TAB tape leads to contacts on a substrate. The method includes separating the electrical leads adjacent the weld bonds leaving a remnant, engaging the remnant with a shear tool, and moving the tool and bond relative to each other shearing the remnant. In some cases the tool is ultrasonically vibrated in a direction transversely to the relative movement of the tool and bond.

Abstract: The excise and lead form of TAB leads bonded to an integrated circuit chip. Leads extending beyond a sidewall are clamped between a first clamp and a form anvil at a first portion spaced from the chip. The leads are also clamped between an excise/form tool and a second clamp at a second portion spaced further from the chip than the first portion. An excise blade cuts the leads outside the second portion. Then the excise/form tool, second clamp and excise blade move downwards in a curved path toward the chip to form a first lead corner against the form anvil and a second lead corner against the excise/form tool without splaying or galling the leads.

Abstract: A field emitter device comprising a conductive metal and a diamond emission tip with negative electron affinity in ohmic contact with and protruding above the metal. The device is fabricated by coating a substrate with an insulating diamond film having negative electron affinity and a top surface with spikes and valleys, depositing a conductive metal on the diamond film, and applying an etch to expose the spikes without exposing the valleys, thereby forming diamond emission tips which protrude a height above the conductive metal less than the mean free path of electrons in the diamond film.

Abstract: A method of applying a compound of a metal and a reactive gas onto a surface by depositing a metal from a liquid metal cluster ion source onto said surface in the presence of a gas on the surface to combine with the deposited metal while isolating the gas from the source of the metal cluster ions.

Abstract: A method of electrically testing an electrical component containing a plurality of networks with at least one node. The method uses segmented, charge limiting testing to charge the nodes and detect shorted or disconnected nodes while preventing accumulated charges in the networks from making uncharged nodes appear charged. The method is well suited for voltage contrast electron beam testing of unpopulated high density multichip modules and interconnect substrates.

Abstract: A dielectric substrate is coated with a protective layer and a catalyst film is formed in a laser irradiated predetermined pattern on the protective layer so that during electroless deposition a metal is plated on the catalyst film in the predetermined pattern whether or not the dielectric has unwanted catalytic sites. The protective layer is not removed by the electroless plating bath or prior etch steps but can subsequently be stripped by a separate etch without removing the plated metal or the dielectric from the substrate.

Abstract: A method of manufacturing a multiple element circuit interconnect substrate is provided which provides an optimized routing plan. The routing plan is based upon a multi-dimensional binary data structure having nodes representing each terminal interconnect requirement which is preprocessed to order the required interconnects according to density.

Abstract: A high density, high performance circuit fabricated with a copper/epoxy structure. The circuit is well suited for an integrated circuit interconnect device. Fluorene-containing epoxy resins may be used to obtain certain material and processing advantages over copper/polyimide structures. The circuit structure resides on a substrate which may be ceramic, a semiconductor such as silicon, or, advantageously, a cured epoxy resin.

Abstract: A system for depositing a film on a substrate includes a sputtering system and means for causing the substrate to move through the sputtering system. Embodiments of the present invention employ a cylindrical hollow cathode magnetron sputtering system, which causes the overall film deposition system to be ideally suited for coating elongate cylindrical substrates such as wires and fibers and the like.

Abstract: Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias.