Abstract: An arbitration circuit portion is provided for coordinating first and second radio circuit portions arranged to transmit and/or receive radio signals. The arbitration circuit is arranged to receive a communication request signal from the first radio circuit portion and/or the second radio circuit portion; determine an arbitration outcome based at least partially on said communication request signal; and apply said arbitration outcome to the first and/or second radio circuit portions. The arbitration circuit portion is operable in a normal arbitration mode, in which determining the arbitration outcome comprises determining an input state based at least partially on said communication request signal and determining an arbitration outcome that corresponds to said input state according to a set of arbitration rules; and a first radio priority mode in which the arbitration outcome prioritizes all requests from the first radio circuit portion over requests from the second radio circuit portion.

Abstract: A device comprising: a transceiver operable in a first or second mode and configured to receive packets from a remote device, each packet comprising an indication of whether or not the remote device has a further packet to transmit, wherein: in the first mode the transceiver: (i) sends a polling message in response to receiving the indication of a further packet for transmission; and (ii) listens for that further packet; and in the second mode the transceiver: (i) does not send a polling message in response to receiving the indication of a further packet for transmission; and (ii) listens for packets regardless of whether a received packet indicates that there is a further packet to transmit or not; and a controller configured to monitor an activity level for the transceiver and cause the transceiver to operate in the first or second mode in dependence on the activity level.

Abstract: An integrated-circuit device comprises a physical-unclonable-function (PUF) unit, a secure module, and an interconnect system communicatively coupled to the PUF unit and to the secure module. The device transfers a PUF key from the PUF unit to the secure module, over the interconnect system. In order to do this, the secure module generates a random value. The secure module then sends the random value to the PUF unit. The PUF unit then performs a bitwise XOR operation between the received random value and the PUF key, to generate a masked value. The PUF unit then transfers the masked value over the interconnect system to the secure module. The secure module then unmasks the PUF key by performing a bitwise XOR operation between the received masked value and the random value.

Abstract: The invention provides a direct memory access (DMA) controller. The DMA controller has an address register, a data register and transfer circuitry for transferring data over a bus of a computing system. The DMA controller is configured to use the transfer circuitry to read data over the bus from a memory location having a first memory address, wherein the data comprises a second memory address, and store the second memory address in the address register, and use the transfer circuitry to transfer data over the bus between a memory location having the second memory address, or having a memory address derived from the second memory address, and the data register.

Abstract: A method and system for moving data from a source memory to a destination memory by a processor is disclosed herein. The destination memory stores a sequence of instructions and the sequence of instructions comprises one or more load instructions and one or more store instructions. The processor initially moves the one or more store instructions from the destination memory to the source memory. The processor then executes the one or more load instructions from the destination memory. On executing the one or more load instructions, the data is loaded from the source memory to at least one register in the processor. The processor further initiates execution of the one or more store instructions stored in the source memory. On executing the one or more store instructions from the source memory, the processor stores the data from the at least one register to the destination memory.

Abstract: A receiver comprises a matched filter bank, decision logic and a frequency offset estimator. The matched filter bank comprises an input for receiving data representative of a frequency- or phase-modulated signal. The decision logic generates a sequence of demodulated symbol values from outputs of the matched filter bank. The frequency offset estimator determines a first phase value from a first output and a second phase value from a second output of the matched filter bank, the second output being offset from the first by L symbol periods. It also determines a phase adjustment value from an L-symbol subsequence within the sequence of demodulated symbol values, each subsequence value being determined from values output by the matched filter bank between the first and second outputs. It estimates a frequency offset based on the difference between the first phase value plus the phase adjustment value, and the second phase value.

Abstract: A method for the protection of files is performed on an integrated-circuit device that comprises a hardware memory protection module, which controls access to regions of the memory depending on region-specific settings. A new file is created in the memory by storing metadata and content data for the new file in a common memory region. An access condition is set for the common memory region in the configuration settings of the hardware memory protection module. A file is retrieved from the memory by searching the memory to identify a file meeting a search criterion. The searching involves comparing the metadata of files from the memory against the search criterion in order to identify a file from the memory that meets the search criterion.

Abstract: A configurable radio frequency receiver is provided. The receiver has at least one low noise amplifier; an oscillator arrangement for producing a plurality of signals having a first number or a second number of separate phases; and multiple mixer modules having inputs connected to an output of the low noise amplifier. The receiver has a configurable resistor network. The receiver is configured such that it can operate in a first mode with said plurality of signals having said first number of phases or a second mode with said plurality of signals having said second number of phases. The configurable resistor network enables the receiver to operate in the first mode in a first configuration, and the second mode in a second configuration. The mixer modules are employed during the operation of the first mode and the second mode.

Abstract: Analog to digital conversion circuitry has an input sampling buffer, which has an input sampling capacitor for sampling an analog signal. The conversion circuitry also has a successive-approximation-register analog to digital converter (SAR-ADC) which converts the sampled analog signal to a digital signal. The input sampling buffer has an amplifier and a gain-control capacitor, and has an amplification configuration and an error-feedback configuration. In the amplification configuration, the input sampling capacitor is coupled to the amplifier and gain-control capacitor, with the gain-control capacitor connected in feedback with the amplifier, for applying gain to the sampled analog signal.

Abstract: A method and system for moving data from a source memory to a destination memory by a processor are disclosed. The processor has a plurality of registers and the source memory stores a sequence of instructions that include one or more load instructions and one or more store instructions. The processor moves the load instructions from the source memory to the destination memory. Then, the processor initiates execution of the load instructions from the destination memory in order to load the data from the source memory to one or more registers in the processor. Execution then returns to the sequence of instructions stored in the source memory, and the processor stores the data from the registers to the destination memory.

Abstract: A radio receiver device is disclosed. The radio receiver device is configured to receive a radio signal comprising a data packet, said data packet comprising a first portion comprising an encoded bit sequence and including information specific to the data packet and a second portion comprising an encoded bit sequence and comprising corresponding information specific to the data packet. The radio receiver device is configured to calculate a correlation metric using the first portion and the second portion; and to estimate a carrier frequency offset between the radio signal and the radio receiver device using the correlation metric.

Abstract: An integrated-circuit device comprises a resettable source register in a first reset domain. A destination circuit, outside the first reset domain, is arranged to sample an output of the resettable source register. A digital logic module causes a central reset controller to output a reset-warning signal in response to receiving a request to reset first reset domain, and to reset the first domain after a predetermined delay period from outputting the reset-warning signal.

Abstract: A receiver apparatus is configured to receive a radio-frequency signal comprising a first subcarrier comprising first subcarrier symbols and a second subcarrier comprising second subcarrier symbols, wherein the first subcarrier symbols and the second subcarrier symbols both encode a same bit sequence in a respective first subcarrier symbol and a second subcarrier symbol. Soft-output decoder logic calculates respective log-likelihood ratios for each of the first subcarrier symbols and generates a first output sequence comprising the respective log-likelihood ratios calculated for the first subcarrier symbols and similarly generates a second output sequence.

Abstract: A receiver apparatus for receiving an OFDM radio signal comprising a first plurality of subcarrier-symbols, modulated on a corresponding plurality of subcarriers, and a second plurality of subcarrier-symbols, modulated on the corresponding plurality of subcarriers, to generate first and second bit sequences, the first bit sequence being an interleaved version of the second bit sequence according to a predetermined interleave function. Soft-output decoder logic generates a first soft-bit sequence for the first plurality of subcarrier-symbols, and a second soft-bit sequence for the second plurality of subcarrier-symbols. Combiner logic combines the soft-bit sequences, with the soft-bit sequences either both in an interleaved state or both in a non-interleaved state, by combining a respective soft-bit having a bit position in the first soft-bit sequence with a respective soft-bit having a same bit position in the second soft-bit sequence.

Abstract: A radio receiver tunes a radio channel by generating a periodic signal, mixing the periodic signal with received radio signals and passing the mixed signal through a channel filter that has a passband that corresponds to the bandwidth of the tuned channel. The receiver receives allocation information identifying a set of subcarriers in the tuned channel on which to receive an OFDM data signal. It uses this information to receive the OFDM data, modulated on the allocated subcarriers. When the allocated subcarriers span an allocated frequency range that is less than the width of the tuned channel and that is offset from the centre of the tuned channel in an offset direction, the receiver offsets the channel filter from the centre of the tuned channel in the offset direction such that the channel filter passes i) said OFDM data signal, ii) an in-allocation reference signal, and iii) an out-of-channel reference signal.

Abstract: There is provided a method of testing an RF transceiver circuit and an RF transceiver circuit arranged to be operable in a test mode comprising a transmitter circuit portion and a receiver circuit portion, the receiver circuit portion including a mixer. The method involves the transmitter circuit portion generating a modulated signal and the receiver circuit portion receiving a continuous radio frequency wave. The mixer mixes the modulated signal with a signal derived from the continuous radio frequency wave to produce an output. A remainder of the receiver circuit portion processes the output of the mixer.

Abstract: An oscillator arrangement is provided, comprising a relaxation oscillator having an active state and an inactive state; a bias current circuit portion arranged to provide a bias current to the relaxation oscillator during said active state; and an electronic switch arranged to isolate said relaxation oscillator from the bias current circuit portion when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current and the bias current circuit portion is arranged to use the stored internal voltage value to generate the bias current when the oscillator is started up from the inactive state to the active state.

Abstract: A control portion for controlling an amplifier portion of a transmitter device is provided. The amplifier portion is arranged to amplify a radio signal with a transmission gain based at least partially on a gain control signal and having a nominal gain relationship between the gain control signal and the transmission gain. The control portion is arranged to determine a desired transmission gain, to determine one or more operating conditions, to calculate a gain control signal for causing the amplifier portion to apply the desired transmission gain, taking into account the nominal gain relationship and the one or more operating conditions, and to output said gain control signal. The gain control signal is different to a gain control signal calculated based only on the nominal gain relationship.

Abstract: A method of digital radio communication between a first device and a second device is disclosed. An advertising packet is transmitted between first and second devices, wherein the packet includes a first address and a data portion. Additionally, an encryption key is transmitted between the devices. The first device generates a second address by encrypting an identity value derived from part of the first address using the encryption key and the data portion. The result is encrypted to generate second portion of the second address. The first device then transmits a connection request including the second address. The second device decrypts the second portion and uses the encryption key to determine correspondence with the first portion. If said correspondence is determined, the second device decrypts the first portion using at least the encryption key and compares it to an expected identity value derived from the first address.

Abstract: An electronic device comprising a system on chip and an external module. The system on chip includes a plurality of internal subsystems and a power management system including a plurality of internal voltage regulators which supply power to the plurality of internal subsystems. Each of the internal voltage regulators has an associated current limiter. The external module includes at least one external voltage regulator which can provide power to at least one of the internal subsystems. The power management system during a start-up phase enables the internal voltage regulators and the current limiters and in a subsequent phase determines an externally powered set of the internal subsystems, disables the corresponding internal voltage regulators, and disables the current limiters associated with the internal subsystems not externally powered.