Abstract: A computer system configured to enable communication between two or more virtual platforms is disclosed. The computer system comprises a physical processor configured to run the two or more virtual platforms. The computer system further comprises a memory. The memory comprises one or more separate memory portions allocated to each of the two or more virtual platforms, wherein within at least one memory portion allocated to one of the virtual platform a predefined range of addresses is configured as a shared device memory, the shared device memory being accessible by all the virtual platforms. Firmware running on a first virtual platform is configured to transfer a data packet from the first virtual platform to one or more further virtual platforms via the shared device memory.

Abstract: An electronic device comprises an oscillator circuit portion comprising an inverter and a crystal oscillator connected between the input and output terminals of the inverter. An amplitude regulator circuit portion is arranged to supply a current to the inverter. The amplitude regulator monitors a voltage at the input of the inverter and varies the current supplied to the inverter in response to the monitored voltage. The amplitude regulator comprises a trimmable resistor arranged such that the voltage at the input of the inverter is set to an operating point when the supply current is equal to a threshold value, the operating point being at least partly determined by the selected resistance of the resistor. A current monitor is arranged to monitor the current supplied to the inverter during operation and to determine therefrom whether the voltage at the input terminal of the inverter is within a predetermined range.

Abstract: A method of determining a distance between a radio frequency device and a target is disclosed in which the radio frequency device receives a radio frequency signal from the target. The method comprises determining a time domain channel response from the received radio frequency signal, determining an amplitude of a largest peak in the time domain channel response, determining an amplitude of a second, earlier, peak in the time domain channel response, comparing the second peak amplitude to a threshold based on the largest peak amplitude, identifying the largest peak as a shortest path peak if the second peak amplitude is less than the threshold, identifying the second peak as a shortest path peak if the second peak amplitude is greater than the threshold, and calculating the distance between the radio frequency device and the target based on a time corresponding to the shortest path peak.

Abstract: A circuit portion comprises a DCDC converter that provides current to one of a plurality of loads at a time. A controller detects when a voltage across an under-supplied load of the plurality of loads is below a first threshold. Channel logic circuitry provides current from the converter to the under-supplied load in response to the controller detecting that the voltage is below the first threshold. A voltage regulator provides current to the under-supplied load when the voltage is below a second threshold.

Abstract: An electronic device comprises a bridge configured to transfer data bus transactions from a transaction source domain having a first bus width to a transaction target domain having a second bus width less than the first bus width. The bridge comprises a first interface configured to receive a transaction from the transaction source domain, where the transaction has a first transaction burst length. A converter logic is configured such that when a transaction is received via the first interface, the converter logic splits the transaction into a plurality of second transactions each having a respective second transaction burst length, wherein the plurality of second transactions have the second bus width. A second interface is configured to send the plurality of second transactions to the transaction target domain.

Abstract: A constant-gm current source, arranged to generate a supply current for a Pierce oscillator. First and second transistors have source terminals connected to first and second supply rails, respectively, and drain terminals connected together and to the gate terminal of the first transistor. Third and fourth transistors have source terminals connected to the first and second supply rails, respectively, and drain terminals are connected together and to the gate terminal of the fourth transistor. An output portion varies the supply current in response to a voltage at the drain terminals of the third and fourth transistors. The gate terminals of the first and third transistors are connected together, and the gate terminals of the second and fourth transistors are connected together. An auto-calibration transistor has its source terminal connected to the first supply rail and its drain terminal connected to the source terminal of the first transistor.

Abstract: A common-mode feedback circuit for a fully differential amplifier comprises first (MB), second (MTP), and third (MTN) transistors, each having a respective drain, source, gate, and back-gate terminals. The drain terminal of the first transistor (MB) and the gate terminals of the first, second, and third transistors (MB, MTP, MTN) are connected together at a bias current terminal. The drain terminals of the second and third transistors are connected together at a tail current terminal. The source terminals of the first, second, and third transistors are connected together. The back-gate terminal of the first transistor (MB) is arranged to receive a common-mode reference voltage input (VCM), the back-gate terminal of the second transistor (MTP) is arranged to receive a positive output voltage (VP) from the fully differential amplifier, and the back-gate terminal of the third transistor (MTN) is arranged to receive a negative output voltage (VN) from the fully differential amplifier.

Abstract: A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

Abstract: A circuit portion is provided which includes an energy harvesting device producing a DC output; a DC-DC converter having an input connected to the DC output of the energy harvesting device; an output for connection to a load; and a monitoring module including a non-ohmic semiconductor element. The monitoring module is arranged to derive information relating to an output current flowing from the DC-DC converter by measuring a current through the non-ohmic semiconductor element. The monitoring module is arranged to adjust one or more parameters of the DC-DC converter based on the information relating to said output current flowing from the DC-DC converter.

Abstract: A method of controlling an electronic device including a memory and a removable smart card. The method involves the device sending a request for context data to the smart card. The smart card sends context data to the device in response to the request and stores this data in the memory and power to the smart card is reduced. Power to the smart card is then increased or restored, and the data is written back to the smart card.

Abstract: A transmitter device includes a power supply, a power supply assessment module, a transmission power assessment module, and a data transmission module. The power assessment module assesses the present power delivery capability of the power supply. The transmission power assessment module assesses the power required for successful data transmission to an external communication party. The transmitter device compares the present power delivery capability to the power required for successful data transmission. If the comparison indicates that the present power delivery capability of the power supply is such that the power supply is able to supply sufficient power for successful data transmission, the transmitter device initiates data communication. If the comparison indicates that the present power delivery capability of the power supply is such that the power supply is not able to supply sufficient power for successful data transmission, the transmitter device does not initiate data communication.

Abstract: A circuit portion is provided which includes an energy harvesting device producing a DC output; an inductor-less capacitor-based DC-DC converter, having an input connected to the DC output of the energy harvesting device; an output connected to a battery; and a voltage limiting module. The voltage limiting module includes a voltage sensor arranged to measure a voltage representative of a voltage at the battery and is arranged to limit a voltage provided by the DC-DC converter if the voltage representative of the voltage at the battery exceeds a threshold.

Abstract: A method of operating a radio receiver device comprises receiving a plurality of signals with a plurality of corresponding frequencies; applying respective gains to each of the plurality of signals; and storing the gain applied to each signal and its corresponding frequency. The method comprises subsequently receiving a further signal with a further frequency; and applying a further gain to the further signal. The further gain is determined using at least one of the stored gains according to a difference between the further frequency and at least one of the plurality of corresponding frequencies.

Abstract: A radio apparatus correlates signal data with stored synchronization data to determine correlation data. The signal data represents a received radio-frequency signal that encodes a data frame, which has a synchronization preamble with a plurality of instances of a predetermined synchronization sequence. The stored synchronization data represents the predetermined synchronization sequence. The radio apparatus identifies a set of peaks in the correlation data, and uses a timing criterion to identify a plurality of subsets of the set of peaks, such that time values of the peaks of each identified subset satisfy the timing criterion. The radio apparatus calculates a correlation score Cj for each of the identified subsets from correlation values of the subset's peaks, and uses the correlation scores Cj to select a subset from the plurality of subsets. Timing or frequency synchronization information for the radio apparatus is determined from the peaks of the selected subset.

Abstract: A bootloader comprises software instructions for execution by a processor of an electronic processing device. The bootloader comprises an interpreter for interpreting a boot script stored in a memory of the processing device, and an integrity checker for checking the integrity of boot scripts stored in the memory. The bootloader comprises instructions for using the integrity checker to check the integrity of a first boot script of a plurality of boot scripts stored in the memory. The bootloader also comprises instructions for using the integrity checker to check the integrity of a second boot script of the plurality of boot scripts stored in the memory, independently of the integrity of the first boot script. The interpreter comprises instructions for interpreting a control-flow command in the first boot script, the control-flow command conditionally or unconditionally causing the bootloader to start interpreting commands from the second boot script.

Abstract: A method of operating a digital radio receiver is provided as follows: a) receiving a radio signal comprising a symbol sequence; b) selecting a portion of the symbol sequence; c) determining a first error between the selected portion of the symbol sequence and a first predetermined symbol sequence using a difference metric; d) determining a set of second errors between the selected portion of the symbol sequence and a respective set of second predetermined symbol sequences, each formed by prepending different length portions of a predetermined preamble symbol sequence to a beginning of the first predetermined symbol sequence; and e) determining a minimum error from the first error and the set of second errors. If the first error is not the minimum error, a different portion of the symbol sequence is selected. Otherwise, a following portion of the symbol sequence is decoded to produce a data payload.

Abstract: An electronic device comprises a synchronisation system that receives a signal clocked by a first clock signal having a first frequency and receives a second clock signal having said first frequency, but offset in phase from the first clock signal. The signal is delayed by an adjustable delay period. It is determined whether, following a logic transition in the delayed signal, the next clock edge received is an active edge or is a non-active edge. A calibration controller increases the delay period when the next clock edge is a non-active edge and maintains or decreases the delay period when the next clock edge is an active edge, or decreases the delay period when the next clock edge is an active edge and maintains or increases the delay period when the next clock edge is a non-active edge.

Abstract: A processing apparatus has a processor comprising a plurality of deferred-push processor registers and processor-register control circuitry. The processor-register control circuitry comprises a plurality of status registers, each status register corresponding to a different respective deferred-push register. The processor-register control circuitry is configured to: detect a write of a new value to a register of the deferred-push registers; and determine whether the status register for the deferred-push register has a first value, indicative of an unsaved status for the deferred-push register. The processor-control circuitry is configured, when the status register has the first value, to: read a current value from the deferred-push register before the writing of the new value to the deferred-push register completes; write the current value to a memory; and set the status register for the deferred-push register to a second value, indicative of a saved status for the deferred-push register.

Abstract: A radio receiver device comprises an analogue-to-digital converter clocked by a first clock signal which receives a radio signal. A digital circuit portion receives a digital signal produced by the analogue-to-digital converter and comprises digital processing units clocked by a second clock derived from the first clock and which produce an output signal at an output sample rate. A counter clocked by the second clock counts samples at the output sample rate. A network timer clocked by a reference of a network clock produces a receiver enable flag synchronised to the first clock. The counter is enabled when the flag is set and sets a trigger flag when the count exceeds a predetermined threshold. A buffer receives the output signal and is enabled when the trigger flag is set.

Abstract: An apparatus for demodulating a frequency-modulated signal comprises a joint frequency-offset & modulation-index estimator, and a signal demodulator. The joint estimator receives data representative of a preamble portion of the signal, modulated with predetermined preamble data. It jointly determines a frequency-offset estimate and a modulation-index estimate by using an optimization process that minimizes a cost function that is a function of the received data and that is parameterised by a frequency-offset parameter and by a modulation-index parameter. The signal demodulator receives data representative of a message portion of the signal, modulated with message data, and uses the frequency-offset estimate to demodulate the message.