Abstract: A method of operating a digital radio transmitter device in accordance with a predetermined communication protocol defining a transmission timing tolerance. The method comprises: transmitting a plurality of first periodic transmissions in accordance with said predetermined communication protocol having a first period and an inherent timing uncertainty less than said transmission timing tolerance; performing a plurality of second periodic actions with a second period wherein said first and second periods are equal to each other or an integer multiple of each other; and adjusting a timing of one or more of the first periodic transmissions by an amount greater than said inherent timing uncertainty but less than or equal to a difference between said inherent timing uncertainty and said transmission timing tolerance so as to change said first period temporarily by an amount less than or equal to said transmission timing tolerance, thereby changing an offset between said first transmissions and said second actions.

Abstract: A clock selector circuit includes a first input for receiving a reference clock signal having a reference frequency, a second input for receiving an offset clock signal having an offset frequency, a clock output for outputting the reference or offset clock signal, and switching circuitry. The switching circuitry includes a switching input and sign detector circuitry that outputs a sign signal indicating whether the reference clock signal is leading the offset clock signal in phase. In response to receiving a switching signal, the switching circuitry detects when like edges of the reference clock signal and the offset clock signal are aligned to within a predetermined tolerance, with the new signal leading the current signal if the offset frequency is lower than the reference frequency, or with the new clock signal trailing the current clock signal if not. In response, the switching circuitry switches to outputting the new clock signal.

Abstract: A method and system for moving data from a source memory to a destination memory by a processor are disclosed. The processor has a plurality of registers and the source memory stores a sequence of instructions that include one or more load instructions and one or more store instructions. The processor moves the load instructions from the source memory to the destination memory. Then, the processor initiates execution of the load instructions from the destination memory in order to load the data from the source memory to one or more registers in the processor. Execution then returns to the sequence of instructions stored in the source memory, and the processor stores the data from the registers to the destination memory.

Abstract: A method and system for moving data from a source memory to a destination memory by a processor is disclosed herein. The destination memory stores a sequence of instructions and the sequence of instructions comprises one or more load instructions and one or more store instructions. The processor initially moves the one or more store instructions from the destination memory to the source memory. The processor then executes the one or more load instructions from the destination memory. On executing the one or more load instructions, the data is loaded from the source memory to at least one register in the processor. The processor further initiates execution of the one or more store instructions stored in the source memory. On executing the one or more store instructions from the source memory, the processor stores the data from the at least one register to the destination memory.

Abstract: A device comprising: a transceiver operable in a first or second mode and configured to receive packets from a remote device, each packet comprising an indication of whether or not the remote device has a further packet to transmit, wherein: in the first mode the transceiver: (i) sends a polling message in response to receiving the indication of a further packet for transmission; and (ii) listens for that further packet; and in the second mode the transceiver: (i) does not send a polling message in response to receiving the indication of a further packet for transmission; and (ii) listens for packets regardless of whether a received packet indicates that there is a further packet to transmit or not; and a controller configured to monitor an activity level for the transceiver and cause the transceiver to operate in the first or second mode in dependence on the activity level.

Abstract: A circuit portion for a radio transceiver comprises: a power amplifier for use when the transceiver operates in a transmission mode, a low-noise amplifier for use when the transceiver operates in a reception mode, a voltage control circuit portion, and a transformer. The transformer comprises a primary winding with a terminal for connecting to an antenna, and a secondary winding comprising a first terminal, a second terminal and a third terminal located between the first and second terminals. The power amplifier is connected to the secondary winding, the low-noise amplifier is connected to both the primary and secondary windings and the voltage control circuit portion is connected to the third terminal of the secondary winding. The voltage control circuit portion applies a first voltage to the third terminal when the transceiver operates in the transmission mode and applies a second, different voltage when the transceiver operates in the reception mode.

Abstract: An integrated-circuit radio transmitter chip comprises a transmitter, a cryptographic engine and control circuitry for the cryptographic engine. The cryptographic engine performs a cryptographic operation by receiving input data, performing a first process to generate first result data and a second process to generate second result data. The first and second result data are used to generate output data. In response to determining that the transmitter is active, the control circuity controls the cryptographic engine to perform the first process and prevents the cryptographic engine from performing the second process while the transmitter is active. The control circuitry controls the cryptographic engine to perform the second process in response to determining that the transmitter is not active.

Abstract: A radio receiver comprises a matched filter bank and a decision unit. The matched filter bank has a plurality of filter modules for generating correlation-strength data from a sampled radio signal, each filter module being configured to cross-correlate the sampled signal with data representing a respective filter sequence. The decision unit is configured to use the correlation-strength data to generate a sequence of decoded symbols from the sampled signal. The matched filter bank and/or decision unit are configured to determine the value of each symbol in the sequence in part based on the value of a respective earlier decoded symbol from the sequence of decoded symbols.

Abstract: A system for synchronizing communications in a radio ranging process involves transmitting calibration signals according to a predetermined schedule of nominal transmission times. Timing offsets are determined. A start time is determined for a transmission of a ranging signal. The start time is earlier than a nominal start time of the ranging signal by at least the largest timing offset. Another system for synchronization involves a radio device transmitting a calibration signal to a second radio device and receiving a calibration response signal from the second radio device. A time-of-flight value is determined in dependence on a time of departure of the calibration signal and a time of arrival of the calibration response signal. A ranging signal is transmitted at a time determined in dependence on the determined time-of-flight value. A ranging response signal is received and processed to determine a range value.

Abstract: An electronic device comprising a system on chip and an external module. The system on chip includes a plurality of internal subsystems and a power management system including a plurality of internal voltage regulators which supply power to the plurality of internal subsystems. Each of the internal voltage regulators has an associated current limiter. The external module includes at least one external voltage regulator which can provide power to at least one of the internal subsystems. The power management system during a start-up phase enables the internal voltage regulators and the current limiters and in a subsequent phase determines an externally powered set of the internal subsystems, disables the corresponding internal voltage regulators, and disables the current limiters associated with the internal subsystems not externally powered.

Abstract: A method of operating a radio receiver to receive downlink control information from a wireless network over a physical downlink control channel, said method comprising receiving a plurality of downlink control information prospect signals; decoding at least one of said prospect signals to produce a prospect sequence; reading a declared repetition level from said prospect sequence; comparing said declared repetition level with a repetition level specified in a predetermined format hypothesis for said downlink control information to determine whether a match exists; if said match exists, storing at least part of said prospect sequence as a prospect stored portion; and subsequently deriving said downlink control information from a prospect stored portion and using said downlink control information in further communications.

Abstract: A radio receiver device determines whether a digital radio signal includes a predetermined cyclic preamble. An input portion samples the digital radio signal and generates a plurality of samples for storage in a buffer. A first autocorrelator correlates first and second subsets of the samples to generate a first correlation metric, the second subset having been stored in the buffer earlier than said first subset by an even integer multiple of half of the preamble period. A second autocorrelator correlates first and third subsets of the plurality of samples to generate a second correlation metric, the third subset having been stored in the buffer earlier than said first subset by an odd integer multiple of half of the preamble period. A processing portion calculates a difference between the correlation metrics and determines that the radio signal includes the predetermined cyclic preamble when the difference is greater than a threshold value.

Abstract: A clock selector circuit receives a first input clock signal (CLK1) having a first frequency, and a second input clock signal (CLK2) having a second frequency. A phase difference detector is configured to detect when a phase difference occurs, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using when a clock edge crosses zero, and to signal this zero crossing to switching circuitry. The switching circuitry is configured, in response to receiving a zero-crossing signal from the phase difference detector, to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch an output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).

Abstract: An oscillator arrangement is provided, comprising a relaxation oscillator having an active state and an inactive state; a bias current circuit portion arranged to provide a bias current to the relaxation oscillator during said active state; and an electronic switch arranged to isolate said relaxation oscillator from the bias current circuit portion when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current and the bias current circuit portion is arranged to use the stored internal voltage value to generate the bias current when the oscillator is started up from the inactive state to the active state.

Abstract: A method of operating a radio receiver device comprises receiving a plurality of signals with a plurality of corresponding frequencies; applying respective gains to each of the plurality of signals; and storing the gain applied to each signal and its corresponding frequency. The method comprises subsequently receiving a further signal with a further frequency; and applying a further gain to the further signal. The further gain is determined using at least one of the stored gains according to a difference between the further frequency and at least one of the plurality of corresponding frequencies.

Abstract: An integrated-circuit device comprises a processor, a hardware key-storage system, and a key bus. The hardware key-storage system comprises a non-volatile key storage memory, which includes a key register, for storing a cryptographic key, and an address register, for storing a destination memory address for the cryptographic key. The hardware key-storage system further comprises output logic for sending the cryptographic key over the key bus to the destination memory address, and write-once logic for preventing an address being written to the address register unless the address register is in an erased state.

Abstract: An integrated-circuit device comprises a bus system connected to a processor, a plurality of peripherals, each connected to the bus system, hardware filter logic; and a peripheral interconnect system, separate from the bus system and connected to the peripherals. For each peripheral, the hardware filter logic stores a respective value determining whether the peripheral is in a secure state. The peripheral interconnect system provides a set of one or more channels for signalling events between peripherals. At least one channel is a secure channel or is configurable to be a secure channel. The peripheral interconnect system is configured to allow an event signal from a peripheral in the secure state to be sent over a secure channel and to prevent an event signal from a peripheral that is not in the secure state from being sent over the secure channel.

Abstract: Analog to digital conversion circuitry has an input sampling buffer, which has an input sampling capacitor for sampling an analog signal. The conversion circuitry also has a successive-approximation-register analog to digital converter (SAR-ADC) which converts the sampled analog signal to a digital signal. The input sampling buffer has an amplifier and a gain-control capacitor, and has an amplification configuration and an error-feedback configuration. In the amplification configuration, the input sampling capacitor is coupled to the amplifier and gain-control capacitor, with the gain-control capacitor connected in feedback with the amplifier, for applying gain to the sampled analog signal.

Abstract: A radio receiver comprises a matched filter bank and a decision unit. The matched filter bank has a plurality of filter modules for generating correlation-strength data from a sampled radio signal, each filter module being configured to cross-correlate the sampled signal with data representing a respective filter sequence. The decision unit is configured to use the correlation-strength data to generate a sequence of decoded symbols from the sampled signal. The matched filter bank and/or decision unit are configured to determine the value of each symbol in the sequence in part based on the value of a respective earlier decoded symbol from the sequence of decoded symbols.

Abstract: An integrated circuit device has a processor, a software-trace message handling system, a software-trace message sink peripheral, and a hardware interconnect system. The interconnect system is capable of directing software-trace messages from the processor to the software-trace message handling system, and of directing software-trace messages from the processor to the software-trace message sink peripheral. The software-trace message sink peripheral can present an interconnect delay to the processor, when receiving a software-trace message from the processor, that is equal to or substantially equal to an interconnect delay that the software-trace message handling system would have presented to the processor if the software-trace message handling system were to have received the software-trace message.