Abstract: A hardware accelerator is arranged to perform cipher operations and comprises a first memory area arranged to store a first bit string and a second memory area arranged to store a second bit string. A calculation block is arranged to receive a round key and to perform a function on the first bit string. The function comprises combining the first bit string with the round key to produce a combined bit string and performing a non-linear mapping from the combined bit string to a mapped bit string. An addition block is arranged to add the mapped bit string to the second bit string to produce a resultant bit string. A controller is arranged to receive a control signal and, depending on the state of the control signal, provides the first bit string and the resultant bit string to the appropriate memory area.

Abstract: A method of operating an oscillator circuit comprising a resonator is provided. The method comprises maintaining a resonance of the resonator by a) connecting the resonator to an input voltage (Vbuf) for a first pulse period to charge the resonator only partially towards the input voltage (Vbuf); b) connecting the resonator to a second, lower, voltage for a second pulse period to discharge the resonator at least partially; and repeating steps a) and b) at a rate corresponding to the resonance of the resonator and with a phase corresponding to the resonance of the resonator, so as to maintain the resonance of the resonator.

Abstract: A clock selector circuit receives a first input clock signal (CLK1) having a first frequency, and a second input clock signal (CLK2) having a second frequency. A phase difference detector is configured to detect when a phase difference occurs, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using when a clock edge crosses zero, and to signal this zero crossing to switching circuitry. The switching circuitry is configured, in response to receiving a zero-crossing signal from the phase difference detector, to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch an output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).

Abstract: A hardware accelerator comprises a direct memory access (DMA) system and an array of processing elements (PEs). Each PE comprises two data inputs and two data outputs and can perform a selectable logical or arithmetic operation. The array comprises configurable interconnects for selectively connecting outputs of the PEs to inputs of the PEs. A first data buffer comprises two or more first-edge cyclic registers, for connecting the DMA system to selected data inputs at a first edge of the PE array. A second data buffer comprises two or more second-edge linear or cyclic shift registers, for connecting selected data outputs of a second edge of the PE array to the DMA system.

Abstract: A method of, and apparatus for, demodulating a frequency-modulated signal.

Abstract: A receiver comprises a matched filter bank, decision logic and a frequency offset estimator. The matched filter bank comprises an input for receiving data representative of a frequency- or phase-modulated signal. The decision logic generates a sequence of demodulated symbol values from outputs of the matched filter bank. The frequency offset estimator determines a first phase value from a first output and a second phase value from a second output of the matched filter bank, the second output being offset from the first by L symbol periods. It also determines a phase adjustment value from an L-symbol subsequence within the sequence of demodulated symbol values, each subsequence value being determined from values output by the matched filter bank between the first and second outputs. It estimates a frequency offset based on the difference between the first phase value plus the phase adjustment value, and the second phase value.

Abstract: According to an aspect, there is provided a first radio device comprising means for performing the following. The first radio device transmits, using a connectionless mode, an advertising message. Subsequently, the first radio device receives, from a second radio device at a second reception time instance measured by the first radio device using the connectionless mode, a scan request. The first radio device transmits, to the second radio device, the scan response using the connectionless mode. Finally, the first radio device performs an auxiliary activity involving wireless communication between the first and second radio devices. The performing of the auxiliary activity is initiated at a first starting time defined to occur at a pre-defined time interval following an anchor point corresponding to the second reception time instance or to a subsequent timestamp generated in response to the receiving of the scan request at the second reception time instance.

Abstract: A current limiting circuit portion for limiting an output current of an electronic device includes an input voltage line for receiving an input voltage and a trimming circuit portion. The trimming circuit portion includes a resistive part providing a first resistance that is configurable based on one or more resistance control signals applied thereto, and a condition-tracking part connected in series with the resistive part that includes a condition-tracking transistor, the condition-tracking part providing a second resistance that is dependent on temperature and the input voltage.

Abstract: An asynchronous circuit portion for sampling an input signal is provided. The circuit portion comprises a sampling circuit portion arranged to sample the input signal to generate a sanitized output signal corresponding to the input signal; a comparison circuit portion arranged to compare the sanitized output signal with the input signal and to generate a change signal if the sanitized output signal does not correspond to the input signal; and a control circuit portion arranged to trigger the sampling circuit portion to sample the input signal to generate an updated sanitized output signal, in response to the change signal.

Abstract: A radio device comprises a radio transceiver, a resonator, a temperature measurement unit, a frequency synthesiser and a processing system. A temperature signal from the temperature measurement unit, representative of a measured temperature of the resonator, is used to determine an estimated frequency offset for the resonator at the measured temperature using a model stored in a memory of the processing system that relates frequency offset to temperature. A periodic signal from the resonator is provided to the frequency synthesizer, which, in dependence on the estimated frequency offset, is used to generate a periodic local signal. The radio transceiver receives a radio signal comprising a periodic component at a received signal frequency. An error value representative of a difference between the received signal frequency and a frequency of the periodic local signal is determined and used to update one or more parameters of the model stored in the memory.

Abstract: A method of operating a display system consisting of a plurality of light emitting diodes (LEDs) is disclosed. The LEDs are arranged in a plurality of groups and an integrated circuit provides power to the LEDs through a plurality of output pins connected to respective groups. The integrated circuit selectively determines the states of the output pins to illuminate the groups of LEDs in a repeating sequence such that each group is illuminated for a time dependent on a number of groups and a compensation factor. The compensation factor is dependent on at least a number of LEDs in the group.

Abstract: A radio-frequency modulator apparatus comprises a baseband stage, a mixer stage and a radio-frequency stage. The baseband stage comprises: an input line for receiving an input current representative of a baseband input signal, a baseband transistor that passes some or all of the input current between a first and a second terminal thereof, an electrical connection between the input line and a control terminal of the baseband transistor, and an output line connected to said control terminal. The mixer stage receives a signal from the baseband stage and mixes it with a radio-frequency local-oscillator signal to generate a radio-frequency mixed signal. The radio-frequency stage receives the radio-frequency mixed signal, applies the radio-frequency mixed signal to a control terminal of a radio-frequency transistor causing it to pass a radio-frequency output current between a first and a second terminal thereof, and outputs the radio-frequency output current as an output signal.

Abstract: An integrated-circuit device comprises a processor, a peripheral component, a bus system, connected to the processor and to the peripheral component, and configured to carry bus transactions; and hardware filter logic. The bus system is configured to carry security-state signals for distinguishing between secure and non-secure bus transactions. The peripheral component comprises a register interface, accessible over the bus system, and comprising a hardware register and a direct-memory-access (DMA) controller for initiating bus transactions on the bus system. The peripheral component supports a secure-in-and-non-secure-out state in which the hardware filter logic is configured to prevent non-secure bus transactions from accessing the hardware register of the peripheral component, but to allow secure bus transactions to access the peripheral component.

Abstract: An Orthogonal Frequency-Division Multiplexing digital radio transmitter is arranged to transmit a data packet comprising a plurality of Orthogonal Frequency-Division Multiplexing symbols. At least one of the symbols comprises a plurality of demodulation reference signals in a first plurality of frequency sub-carriers of the symbol. The transmitter is arranged to transmit a physical control channel at least partly distributed among a remainder of frequency sub-carriers of the symbol according to a calculated distribution. The transmitter calculates the distribution by arranging the remainder of frequency sub-carriers in a two-dimensional matrix such that said remainder of frequency sub-carriers have indices which are sequential in a first dimension and have a common increment in a second dimension, and allocating a second plurality of the remainder of frequency sub-carriers to the physical control channel sequentially in the second direction.

Abstract: An electronic device comprises a processor, a memory, a memory controller for controlling access to the memory, a hardware security module, and a bus system, to which the processor, the memory controller, and the hardware security module are connected. The hardware security module uses its connection to the bus system to detect requests on the bus system that are sent by the processor. The hardware security module has a secure state and a non-secure state. When in the secure state, the hardware security module adds a secure-state signal to requests sent by the processor over the bus system. The memory controller determines whether memory-access requests include the secure-state signal, and denies access to a secure region of the memory in response to receiving memory-access requests that do not include the secure-state signal.

Abstract: A time delay circuit comprising a plurality of differential delay cells each having a respective time delay and being arranged in series. Each delay cell comprises first and second inverter sub-cells, each comprising a respective PMOS transistor and an NMOS transistor arranged in series such that their respective drain terminals are connected at a drain node. Each of the transistors has a back-gate terminal and is arranged such that a respective voltage applied to said back-gate terminal linearly controls its respective threshold voltage. The back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell and/or the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell. A control signal varies the time delay of the delay cell by adjusting a voltage supplied to a back-gate terminal of a transistor.

Abstract: A method of digital radio communication between a central device and a peripheral device. The peripheral device transmits a repeated burst of advertising packets on a primary physical channel, each packet comprising an advertising field indicating an availability to form a connection. The advertising field comprises an address identifying the peripheral device. The peripheral device transmits a subsequent advertising packet on an auxiliary channel. The central device receives a packet from the burst of packets, decodes the advertising field and compares the address to one or more desired connection addresses to determine whether to initiate a connection to the peripheral device. If the address matches a desired connection address, the central device initiates a connection to the peripheral device. If the address does not match a desired connection address, the central device resumes listening for further advertising packets.

Abstract: A technique for efficient calling of functions on a processor generates an executable program having a function call by analysing an interface for the function that defines an argument expression and an internal value used solely within the function, and an argument declaration defining an argument value to be provided to the function when the program is run. A data structure is generated including the internal value and a resolved argument value derived from the argument expression and the argument value. A single instruction is encoded in the program to utilise the data structure. When the program is executed on a processor, the single instruction causes the processor to load the argument value and internal value from the data structure into registers in the processor, prior to evaluating the function. The function can then be executed without further register loads being performed.

Abstract: A local oscillator buffer circuit comprises a complementary common-source stage comprising a first p-channel transistor (MCSP) and a first n-channel transistor (MCSN), arranged such that their respective gate terminals are connected together at a first input node, and their respective drain terminals of each of is connected together at a buffer output node. A complementary source-follower stage comprises a second p-channel transistor (MSFP) and a second n-channel transistor (MSFN), arranged such that their respective gate terminals are connected together at a second input node, and their respective source terminals are connected together at the buffer output node.

Abstract: A method of communication between an electronic device and a cellular network employing a communication protocol is disclosed. The device initiates a connection with the network and during the initiation the device issues to the network at least one information criterion. Once the connection is established, the network forwards to the device only communications required by said communication protocol and any communications which meet the information criterion issued by the device.