Abstract: In accordance with a first aspect of the present disclosure, a method is conceived for determining the position of at least one node in a communication network, wherein the communication network comprises a localization system that includes a processing unit, a primary anchor and at least one secondary anchor, the method comprising: the primary anchor transmits a poll message to the node and to the secondary anchor; the primary anchor receives a response message from the node; the secondary anchor receives said poll message from the primary anchor and said response message from the node; the processing unit calculates the position of the node using position information and timing information, wherein said position information is position information of the primary anchor and of the secondary anchor, and wherein said timing information is timing information of the poll message transmission by the primary anchor, of the poll message reception by the node and the secondary anchor, of the response message transmi

Abstract: There is described a hybrid ADC device for converting an analog input signal (Vin) into a digital output signal (Vout), the device comprising a first ADC circuit configured to receive the analog input signal (Vin) and convert it into a first digital signal (Y0); a DAC circuit configured to receive the first digital signal and convert it into a first analog signal; a delay circuit configured to delay the analog input signal; a first combiner configured to generate an analog residual signal by subtracting the first analog signal from the delayed analog input signal; a second ADC circuit configured to receive the residual analog signal and convert it into a second digital signal (Y1); a filter circuit configured to receive the first digital signal and output a filtered first digital signal (Y0?), the filter circuit having a transfer function corresponding to a combined transfer function of the DAC circuit and the second ADC circuit; and a second combiner configured to generate the digital output signal (Vout) by

Abstract: A Controller Area Network (CAN) system, method, and circuit are provided with a dual mode bus line termination circuit connected between signal lines of a serial bus and optimized for both differential and single-ended communication modes over the serial bus, where the dual mode bus line termination circuit includes first and second resistance termination paths connected in parallel between first and second bus wires of the serial bus to provide an odd mode termination impedance (RODD) that matches an impedance of the serial bus when operating in the differential communication mode, and to also provide an even mode termination impedance (REVEN) that matches an impedance of the serial bus when operating in the single-ended communication mode.

Abstract: Aspects of the present disclosure are directed to radar apparatuses and methods involving the communication of data with radar signals. As may be implemented with one or more embodiments, a sequence of radar waveforms are transmitted as RF signals, the RF signals carrying communication data encoded onto a ramped radar carrier signal via phase-shift keying (PSK) modulation. Such modulation may utilize a modified, reduced-angle modulation with phase angles of less than ?. Object-reflected versions of the RF signals are received and demodulated by deramping the received object-reflected versions of RF signals using a linearized version of the radar waveforms (e.g., without PSK modulation). This approach can mitigate compression peak loss.

Abstract: A low power temperature detection method, system, and apparatus sense when a temperature threshold is reached by connecting a current conveyor (111) with a startup bias circuit (112) having a first FET (P1) (connected to level shift a reference voltage to provide an input voltage VS1), a first diode-connected BJT (Q0) (connected to generate a base-emitter voltage based on the junction temperature), and a second FET (P2) (connected to level shift the base-emitter voltage), where the startup bias circuit (112) selectively connects the current conveyor (111) to ground to form a closed loop that is activated only when an emitter current at the first diode-connected BJT (Q0) enters a self-turned-on operation region, thereby activating the current conveyor to detect a temperature threshold being reached by the device junction temperature.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes attaching a first end of a first bond wire to a first conductive lead and a second end of the first bond wire to a first bond pad of a first semiconductor die. A conductive lead extender is affixed to the first conductive lead by way of a conductive adhesive, the lead extender overlapping the first end of the first bond wire. A first end of a second bond wire is attached to the lead extender, the first end of the second bond wire conductively connected to the first end of the first bond wire.

Abstract: One example discloses a near-field interface device, including: a near-field antenna; a physical port configured to be coupled to a computer; a controller coupled to the antenna and the physical port; wherein the controller is configured to translate a near-field signal received from the near-field antenna into an input command generated by a user; and wherein the controller is configured to transmit the input command to the computer through the physical port.

Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.

Abstract: An address fault detection system includes write and read access circuits and a fault management circuit. The write access circuit receives an address and reference data for a write operation associated with a memory and parity data generated based on the reference data, and writes the reference data and the parity data to first and second memory blocks of the memory, respectively. The read access circuit receives the same address for a read operation associated with the memory and reads another reference data and another parity data from the first and second memory blocks, respectively. The fault management circuit compares the read parity data with parity data generated based on the read reference data to detect an address fault in the memory. The written and read reference data are different when the address fault is detected, and same when the address fault is not detected.

Abstract: A combination of machine learning models is provided, according to certain aspects, by a data-aggregation circuit, and a computer server. The data-aggregation circuit is used to assimilate respective sets of output data from at least one of a plurality of circuits to create a new data set, the respective sets of output data being related in that each set of output data is in response to a common data set processed by the machine learning circuitry in the at least one of the plurality of circuits. The computer server uses the new data set to train machine learning operations in at least one of the plurality of circuits.

Abstract: Near field communication (NFC) methods, systems, and devices are disclosed herein. In an example embodiment, the method includes providing a first NFC device including a NFC antenna, and transmitting a radio frequency (RF) signal including a RF carrier signal by way of the NFC antenna. Also, the method includes receiving a first resonant signal after the transmitting has ceased, and processing the first resonant signal to generate a first portion of transformed signal information. Further, the method includes identifying one or both of a first state and a first event based at least in part upon or associated with the first portion of the transformed signal information.

Abstract: Various embodiments relate to a method for multiplying a first and a second polynomial in a ring q [X]/(Xn+1) where q is a positive integer.

Abstract: A method is provided for collecting diagnostic information in a device having a rich execution environment (REE) and a secure element (SE). The method includes detecting initialization of the device. If it is determined that the initialization of the device was a result of a potential security related event, a communication component of the REE responsible for communicating with the secure element is activated if not already activated. The secure element sends a request to the communication component for diagnostic information related to the security event. The diagnostic information is received in the SE from the communication component and stored in an attack log for storing security events. An attack log is generated in the secure element including the potential security event and the related diagnostic information. The attack log and the related diagnostic information is communicated to a secure server via a secure channel.

Abstract: Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader.

Abstract: A mechanism is provided to secure integrated circuit devices that combines a high degree of security with a low overhead, both in area and cost, thereby making it appropriate for smaller, cheaper integrated circuits. A determination is made whether a device die is on a wafer or if the device die is incorporated into a package. Only if the device die is incorporated in a package can the functional logic of device die be activated, and then only if a challenge-response query is satisfied. In some embodiments, a random number generator is used during wafer testing to form a pair of numbers, along with a die identifier, that is unique for each device die. A final test is then performed in which the device die can be activated if the device die is incorporated in a package, and the die identifier—random number pair is authenticated.

Abstract: A Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter (100) comprising: an oscillator (101) configured to generate a clock signal having n equally spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n Digital to Analog Converters, DACs (1021-3), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC being configured to provide an output signal that transitions between first and second output levels in M discrete steps upon being triggered by a transition of a signal on the data input line synchronized with the one of the n phases of the clock signal; and an output amplifier stage (103) configured to provide a differential CAN output signal from a combination of output signals from each of the n DACs (1021-3).

Abstract: Systems and methods for preserving a decoupling capacitor's charge during low power operation of a logic circuit. An electronic circuit may include: a main voltage regulator coupled to a supply voltage terminal and configured to apply a first regulated voltage across a capacitor coupled in parallel with a logic circuit; a low power regulator coupled to the supply voltage terminal and configured to apply a second regulated voltage across the logic circuit; and a control circuit coupled to the low power regulator. The control circuit may be configured to: during a first mode of operation, allow the main voltage regulator to apply the first regulated voltage to the logic circuit, and, during a second mode of operation, allow the low power regulator to apply the second regulated voltage to the logic circuit and decouple the capacitor from the logic circuit while the low power regulator applies the second regulator voltage.

Abstract: A microprocessor system includes a processing circuit and a memory operably coupled to the processing circuit and configured to receive input data according to a pack and store operation and output the data according to a load and unpack operation. The processing circuit comprises a hardware extension configured to: configure a variable number of bits per data element during a pack and store operation; store a concatenation of a plurality of data elements with a reduced number of bits; extract a plurality of data elements with a reduced number of bits during a load and unpacking operation; and recreate a plurality of data elements with an increased number of bits per data element representative of the data elements prior to the pack and store operation.

Abstract: A method and system are provided for supplying power to a backup power domain by connecting a battery voltage to a supply terminal for a backup power domain in a low power microcontroller during a startup mode when a main supply voltage, by detecting application of the main supply voltage to the low power microcontroller at a predetermined safe voltage level, and by activating a selection control circuit to power the backup power domain in the low power microcontroller from the main power supply voltage or the backup power supply voltage based on a software-controlled configuration bit, where the selection control circuit is configured to connect, in response to the software-controlled configuration bit having a first user-selected value, the main power supply voltage to the supply terminal for the backup power domain when the main power supply voltage is smaller than the battery power supply voltage.

Abstract: Aspects of the present disclosure are directed toward apparatuses and/or methods involving the communication of radar signals. Certain aspects involve communicating time division multiplexing (TDM) multi-input multi-output (MIMO) radar signals, having pulses with a chirp interval time (CIT) that is different for respective chirps. Positional characteristics of a target may be ascertained based upon both the CIT between each chirp in the communicated radar signals and the time between each corresponding chirp in received ones of the signals reflected by the target. Communication of the radar signals may involve utilizing a combination of antennas to provide a virtual aperture.