Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.

Abstract: A packaging assembly and methodology provide a PCB substrate with one or more waveguide apertures and a conductive pattern which includes a plurality of landing pads that are disposed around peripheral edges of each waveguide aperture and that are connected to one another by trace lines so that, upon attachment and reflow of solder balls to the plurality of landing pads, the solder balls reflow along the trace lines to form a fully closed solder waveguide shielding wall disposed around peripheral edges of the first waveguide aperture.

Abstract: Semiconductor packages with embedded wiring on re-distributed bumps are described. In an illustrative, non-limiting embodiment, a semiconductor package may include an integrated circuit (IC) having a plurality of pads and a re-distribution layer (RDL) coupled to the IC without any substrate or lead frame therebetween, where the RDL comprises a plurality of terminals, and where one or more of the plurality of pads are wire bonded to a corresponding one or more of the plurality of terminals.

Abstract: Aspects of the present disclosure are directed to radar signal processing apparatuses and methods. As may be implemented in accordance with one or more embodiments, digital signals representative of received reflections of radar signals transmitted towards a target are mathematically processed to provide or construct a matrix pencil based on or as a function of a forward-backward matrix. Eigenvalues of the matrix pencil are computed and an estimation of the direction of arrival (DoA) of the target is output based on the computed eigenvalues.

Abstract: An integrated circuit includes a functional circuit, a detection circuit, a processing circuit, and a recovery circuit. The detection circuit detects a fault in the functional circuit and generates a fault indication indicative of the detected fault. The processing circuit receives the fault indication and identifies a functional domain identifier (ID) associated with the fault. Based on the fault indication, the processing circuit generates context tag data that is indicative of a type of the fault and an operational state of the functional circuit when the fault is detected therein. Further, the processing circuit assigns a priority level to the fault based on the context tag data and the functional domain ID. The recovery circuit performs, based on the functional domain ID, the context tag data, and the first priority level, a recovery operation to recover the functional circuit from the fault.

Abstract: An integrated circuit can comprise an output terminal, a power transistor having a first current electrode coupled to the output terminal and a second current electrode coupled to a power supply terminal, a driver having an output coupled to a control electrode of the power switch, a capacitor having a first terminal coupled to the output terminal and a second terminal coupled to a circuit node, a first low pass filter coupled between the circuit node and an input of the driver, the first low pass filter having a first cut off frequency, a set of current sources, and a second low pass filter coupled between the circuit node and an output of the set of current sources. The second low pass filter can have a second cut off frequency that is higher than the first cut off frequency.

Abstract: A data processing system and a method are provided for recognizing a scanned biometric characteristic in the data processing system. The data processing system includes a biometric sensor, a rich execution environment (REE), and a secure element (SE). In one embodiment, during an enrollment operation, a random challenge is applied to scanned data to produce a biometric template that is stored. During subsequent validation operations, the SE determines if user data includes evidence of the random challenge before providing access to a secure application. Evidence of the random challenge indicates the user data was provided by the biometric sensor. In another embodiment, the sensor data is split between the REE and the SE and partially processed in the SE. The described embodiments prevent a replay attack from being conducted in communications between the REE and the SE.

Abstract: A Controller Area Network, CAN, device comprising: a compare module configured to interface with a CAN transceiver, a CAN decoder configured to decode an identifier of a CAN message received from the RXD input interface; an identifier memory configured to store an entry that corresponds to at least one identifier; compare logic configured to compare a received identifier from a CAN message to the entry that is stored in the identifier memory and to output a match signal upon a match; a signal generator configured to output, in response to the match signal, a signal to invalidate the CAN message, wherein the signal is output from the TXD output interface to the CAN transceiver; and wherein the signal generated by the signal generator provides for one or more dominant bits that are timed so that at a bit immediately following a FDF field or the FDF field bit is made dominant.

Abstract: A calibration system comprises an actuator circuit comprising a first delay circuit that receives a plurality of data pulses and a second delay circuit that receives the pulses, wherein one of the first and second delay circuits delays the data pulses independently of the other of the first and second delay circuits; a data switch that receives an output of the actuator circuit including delay data signals of the data pulses from the first and second delay circuits and switches and outputs a plurality of local oscillator (LO) signals for output as a controlled LO signal according to control signals of the delay data signals and applied to the data switch. At least one calibration switch receives the output of the actuator circuit and the plurality of LO+ and LO? signals, and outputs a second controlled LO signal output to a sense circuit.

Abstract: A linear chirp radar system, apparatus and method use a radar control processing unit to control an LFM radar front end which generates analog-to-digital (ADC) sample signals from one or more target return signals received in response to transmitted linear chirp radar signals, where the radar control processing unit is connected and configured to mitigate range migration by directly filtering the ADC samples using a modified Doppler filter that is tuned to fast-time scaled, slow-time frequencies to generate a focused ADC Doppler cube, and by applying a Fourier Transform on each Doppler cell in the focused ADC Doppler cube to generate a focused range-Doppler cube.

Abstract: Five-side mold protection for semiconductor packages is described. In an illustrative, non-limiting embodiment, a semiconductor package may include: a substrate comprising a top surface, a bottom surface, and four sidewalls; an electrical component comprising a backside and a frontside, where the frontside of the electrical component is coupled to the top surface of the substrate; and a molding compound, where the molding compound encapsulates the backside of the electrical component and the four sidewalls of the substrate.

Abstract: A data processing system includes a rich execution environment, a hardware accelerator, a trusted execution environment, and a memory. The REE includes a processor configured to execute an application. A compute kernel is executed on the hardware accelerator and the compute kernel performs computations for the application. The TEE provides relatively higher security than the REE and includes an accelerator controller for controlling operation of the hardware accelerator. The memory has an unsecure portion coupled to the REE and to the TEE, and a secure portion coupled to only the TEE. The secure portion is relatively more secure than the unsecure portion. Data that is to be accessed and used by the hardware accelerator is stored in the secure portion of the memory. In another embodiment, a method is provided for securely executing an application is the data processing system.

Abstract: In accordance with a first aspect of the present disclosure, a communication device is provided, comprising: a first antenna configured to receive and transmit a first set of near field communication (NFC) signals, wherein said first set of NFC signals relates to NFC transactions; a second antenna configured to receive and transmit a second set of NFC signals, wherein said second set of NFC signals relates to wireless charging operations; a controller; a first interface between the controller and the first and second antenna, the first interface comprising an antenna selection unit configured to select the first antenna or the second antenna in response to a selection signal received from said controller; a second interface between the controller and the first antenna; wherein the controller is configured to detect whether an external communication device is within communication range of the first antenna using the second interface.

Abstract: An electronic circuit is provided. The electronic circuit includes a full-bridge rectifier, a spurious tone detection circuit, and a controller. The rectifier circuit has a plurality of switching elements and first and second radio frequency (RF) terminals. The spurious tone detection circuit has a non-linear circuit element and is coupled between the first RF terminal and a first reference terminal. The spurious tone detection circuit provides a non-zero direct current (DC) voltage in response to detecting harmonic tones at the first RF terminal of the full-bridge rectifier circuit. The controller is coupled to the plurality of switching elements. The controller is for controlling the operation of the plurality of switching elements based at least in part on detecting the harmonic tones. In one embodiment, the electronic circuit may be a wireless charging receiver. In another embodiment, a method for detecting harmonic tones in the electronic device is provided.

Abstract: A mechanism is provided for estimating mounting orientation yaw and pitch of a radar sensor without need of prior knowledge or information from any other sensor on an automobile. Embodiments estimate the sensor heading (e.g., azimuth) due to movement of the automobile from radial relative velocities and azimuths of radar target detections. This can be performed at every system cycle, when a new radar detection occurs. Embodiments then can estimate the sensor mounting orientation (e.g., yaw) from multiple sensor heading estimations. For further accuracy, embodiments can also take into account target elevation measurements to either more accurately determine sensor azimuth and yaw or to also determine mounting pitch orientation.

Abstract: In an embodiment, an integrated circuit die includes a semiconductor substrate, patterned metal layers compiled over the semiconductor substrate, and a tapered multipath inductor formed in the patterned metal layers. The tapered multipath inductor includes, in turn, an inductor input terminal, an inductor output terminal, and N number of parallel inductor tracks electrically coupled between the inductor input terminal and the inductor output terminal. The parallel inductor tracks wind or wrap around an inductor centerline to define a plurality of multipath inductor windings including an innermost winding and an outermost winding. The parallel inductor tracks further vary in track width when progressing from the outermost winding to the innermost winding of the plurality of multipath inductor windings.

Abstract: An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.

Abstract: A Wilkinson power combiner (202) is described that includes: at least one input port (210) coupled to at least one output port (212, 214, 216, 218) by at least two power combining stages. A first power combining stage (204) of the at least two power combining stages is configured as a single-stage first frequency pass circuit and a second power combining stage (206) of the at least two stages is configured as a single-stage second frequency pass circuit, and wherein the first frequency is different to the second frequency.

Abstract: A method is provided for secure provisioning of a device. In the method, a plurality of integrated circuit (IC) devices is manufactured by a first entity for use in the device. The first entity provides signed provisioning software and stores in at least one provisioning IC device one or more keys used for provisioning the plurality of ICs. The provisioning device with the signed provisioning software is provided to a second entity. The second entity verifies the provisioning software using a stored key. The provisioning software encrypts provisioning assets provided by the second entity and provides the encrypted provisioning assets to the third entity. The signed provisioning software is provided to a third entity by the first entity. During manufacturing of the manufactured products by the third entity, the provisioning software verifies and decrypts the encrypted provisioning assets of the second entity to provision all the plurality of IC devices.

Abstract: A data processing system has a processor, a system memory, and a hypervisor. The system memory stores program code and data in a plurality of memory pages. The hypervisor controls SLAT (second level address translation) read, write, and execute access rights of the plurality of memory pages. A portion of the plurality of memory pages are classified as being in a secure enclave portion of the system memory and a portion is classified as being in an unsecure memory area. The portion of the memory pages classified in the secure enclave is encrypted and a hash is generated for each of the memory pages. During an access of a memory page, the hypervisor determines if the accessed memory page is in the secure enclave or in the unsecure memory area based on the hash. In another embodiment, a method for accessing a memory page in the secure enclave is provided.