Abstract: In accordance with a first aspect, a communication device is provided, comprising: a transmitter configured to transmit one or more radio frequency signal pulses to an external communication device; a receiver configured to receive one or more response signals in response to the radio frequency signal pulses transmitted by the transmitter; a signal analyzer configured to detect one or more characteristics of the response signals, to compare the detected characteristics with predefined reference characteristics and to generate an output indicative of a result of comparing the detected characteristics with the predefined reference characteristics; a processing unit configured to determine at least one category to which the external communication device belongs based on the output generated by the signal analyzer. In accordance with a second aspect, a corresponding method of operating a communication device is conceived. In accordance with a third aspect, a corresponding computer program is provided.

Abstract: A system includes a first integrated circuit device, a second integrated circuit device, and a reference clock provided to the first and second integrated circuit devices. The first integrated circuit device detects a first edge of a first clock utilized by the first integrated circuit device, detects a second edge of the first clock, determines a first count of cycles of the reference clock between the first edge and the second edge, and communicates the first count to the second integrated circuit device. The second integrated circuit device receives the first count, provides a third edge of a second clock utilized by the second integrated circuit device, determines that a first number of cycles of the reference clock since providing the third edge is equal to the first count, and provides a fourth edge of the second clock in response to determining that the first number of cycles is equal to the first count.

Abstract: A Controller Area Network, CAN, bit stream sampling apparatus for a CAN controller, the apparatus configured to receive a bit stream from a CAN transceiver, the apparatus configured to: detect rising edges in said bit stream; detect, separately, falling edges in said bit stream; and generate a restored non-return-to-zero coded bit stream based at least on said detected falling edges and said detected rising edges.

Abstract: A linear chirp radar system, apparatus and method use a radar control processing unit to control an LFM radar front end which includes a frequency-scanning transmit antenna and a frequency-scanning receive antenna which respectively sweep a transmit and receive energy focus across an angle space with each linear chirp signal, where the radar control processing unit processes digital output signals generated from target return signals received in response to transmitted linear chirp signals and extracts target range-angle information by applying time-frequency analysis processing to the digital output signals to generate a first range-angle map which includes range-biased angle information, and then applying a group delay compensation process to generate a second range-angle map which includes target range-angle information that is generated by selectively adjusting the range-biased angular information in the first range-angle map with an angular adjustment.

Abstract: A semiconductor device and a method of making the same. The device includes an encapsulant. The device also includes a semiconductor die in the encapsulant. The device further includes electromagnetic radiation transmitting and receiving parts in the encapsulant. The device also includes an intermediate portion having a first surface and a second surface. The first surface is attached to the encapsulant. The device also includes an antenna portion attached to the second surface of the intermediate portion. The antenna portion includes one or more openings for conveying electromagnetic radiation. The intermediate portion includes one or more corresponding openings aligned with the openings of the antenna portion. Each opening of the antenna portion and each corresponding opening of the intermediate portion forms an electrically contiguous passage for conveying the electromagnetic radiation to the electromagnetic radiation transmitting and receiving parts in the encapsulant.

Abstract: A Radio Frequency Identification (RFID) tag is disclosed. The RFID tag includes an antenna to receive a high frequency signal, a capacitor bank coupled with the antenna, a charge pump coupled with the antenna configured to convert the high frequency signal to a direct current (DC) signal, an envelope detector to measure peak voltage of the high frequency signal and a detector to compare an output of the charge pump and an output of the envelope detector. The RFID tag also includes an impedance tuning circuit coupled with the charge pump and the envelope detector configured change a capacitance of the capacitor bank based on an output of the detector and the envelope detector.

Abstract: A method for digital-to-analog signal conversion with distributed reconstructive filtering includes receiving a digital code synchronous to a clock signal having a first frequency, determining next states of a plurality of digital-to-analog current elements based on the digital code, combining a plurality of currents to generate an output current, and generating the plurality of currents. Each of the plurality of currents is based on a corresponding control signal of a plurality of control signals. The method includes generating the plurality of control signals based on the next states of the plurality of digital-to-analog current elements. Each of the plurality of control signals selects a first voltage level, a second voltage level, or a transitioning voltage level for use by a corresponding digital-to-analog current element. The transitioning voltage level linearly transitions from the first voltage level to the second voltage level over a predetermined number of periods of the clock signal.

Abstract: A first anchor of a first type communicates with a mobile electronic device. A characteristic of the communications between the first anchor of the first type and the mobile electronic device is determined. One or more second anchors each of a second type is selected based on the characteristic of the communications. A respective distance to the mobile electronic is determined based on each of the selected one or more second anchors each of the second type.

Abstract: An integrated circuit transformer (150) is formed with a primary winding (91) located in at least a first winding layer having a first thickness, a secondary winding (92) located in at least the first winding layer and having a first center point at the first side of the transformer and two secondary terminals at a second, opposite side of the transformer, and a first center tap feed line (81) located along a symmetry axis of the transformer in an upper metal layer having a second thickness that is at least equivalent to the first thickness of the first winding layer, wherein the first center tap feed line has a direct electrical connection to the first center point in the secondary winding.

Abstract: Various embodiments relate to a free running oscillator, that includes a switch capacitor based frequency-to-voltage converter (F2V), a comparator, and a voltage controlled oscillator (VCO), which may be collectively configured to reduce amplifier offset and flicker noise while increasing effective gain of the amplifier of the comparator. The F2V may produce a feedback voltage Vfb corresponding to frequencies of output of the VCO. The comparator may be configured to sample a reference voltage Vref using a sampling capacitor, compare Vref to Vfb, and generate an output based on any difference between Vref and Vfb, where the output may be integrated using an integrating capacitor of the comparator. The comparator may compensate for parasitic capacitance at the output of the amplifier by using an amplifier having two outputs, with the sampling capacitor and integrating capacitor being coupled to respectively different outputs of the amplifier.

Abstract: A method of estimating a clock frequency offset in a mobile device relative to a clock frequency of a controller within a UWB network comprises (a) determining, for each of a plurality of anchors, an anchor clock frequency offset relative to the controller clock frequency, (b) broadcasting an anchor data packet from each anchor, the anchor data packet including the respective anchor clock frequency offset, (c) receiving at least one anchor data packet at the mobile device, (d) estimating a mobile device clock frequency offset relative to the anchor clock frequency of the anchor from which the at least one anchor data packet was received, and (e) estimating the clock frequency offset in the mobile device based on the estimated mobile device clock frequency offset and the anchor clock frequency offset included in the at least one received anchor data packet. Furthermore, a TDoA-based localization method and a TDoA-based localization system are described.

Abstract: The disclosure relates to a switched capacitor converter (SCC) with gate driving circuits for limiting currents provided by switching field effect transistors. Embodiments disclosed include an SCC with gate driver curcuits providing gate voltage signals to power FETs, each gate driver circuit comprising first and second gate driver modules and configured to operate in: a first mode in which the first gate driver module provides a gate voltage signal to a power FET that switches between first and second voltage rails by operation of first and second switches connected between the pair of voltage rails; and a second mode in which, in reponse to enabling of a current limit switching signal, the first gate driver module disables switching of one of the first and second switches and the second gate driver module operates to limit a current provided to the power FET.

Abstract: An integrated circuit includes an analog-to-digital converter (ADC) configured to receive input voltage, and first and second reference voltages, and outputs digital code representing ratios between the input voltage and the first and the second reference voltages. The first and second reference voltages are generated by a reference generator using different current densities. During a first stage, the ADC samples the first input voltage and the first reference voltage and transfers equivalent charge of the sampled first input voltage and first reference voltage to an integration capacitor. During a second stage, the ADC samples the second reference voltage and transfers equivalent charge of the sampled second reference voltage to the integration capacitor. The ADC provides one bit of digital code based on total charge stored on the integration capacitor after the transfers of charge of the sampled input voltage, and the sampled first and second reference voltages.

Abstract: In accordance with a first aspect of the present disclosure, an ultra-wideband communication node is provided, comprising: an ultra-wideband communication unit configured to transmit one or more messages to a plurality of external responder nodes and to receive one or more responses from said responder nodes; a processing unit configured to use a common cryptographic session key to encrypt said messages, wherein said common cryptographic session key is a key shared between the ultra-wideband communication node and all the external responder nodes; wherein the processing unit is further configured to use responder-specific cryptographic session keys to decrypt the responses and/or to encrypt further messages to the responder nodes, and wherein each individual one of said responder-specific cryptographic session keys is a key shared between the ultra-wideband communication node and one of the external responder nodes.

Abstract: A circuit module including an integrated circuit (IC) and a method for forming an IC are disclosed. An embodiment of the circuit module includes a trench having a conductive trench liner formed in a semiconductor substrate, and further includes semiconductor device circuitry formed in the substrate, where a conductor within a metallization layer of the semiconductor device circuitry electrically connects to the conductive trench liner. The embodiment also includes an insulating structure arranged over the conductive trench liner, where the insulating structure extends to an upper contact formed within an upper metallization layer of the semiconductor device circuitry. An isolation capacitor operable between the upper contact and the conductive trench liner has one or more electrical properties dependent on both a depth of the trench and a number of metallization layers below the upper metal layer in the semiconductor device circuitry.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes depositing a non-conductive layer over a semiconductor die. An opening is formed in the non-conductive layer exposing a portion of a bond pad of the semiconductor die. A cavity is in the non-conductive layer with a portion of the non-conductive layer remaining between a bottom surface of the cavity and a bottom surface of the non-conductive layer. A conductive layer is formed over the non-conductive layer and the portion of the bond pad. The conductive layer is configured to interconnect the bond pad with a conductive layer portion over the cavity.

Abstract: Embodiments of a multithreaded processor and a method of assigning blocks of register files for hardware threads of multithreaded processors are disclosed.

Abstract: A Controller Area Network, CAN, transceiver comprising: two terminals for coupling to a CAN bus; a transmitter arrangement configured to transmit signalling on the bus based on transmit data, the transmitter arrangement configured to drive the bus to a dominant state or recessive state based on the transmit signal; an impedance control device; a signalling detector to determine the length of time the transmit data comprises a logic zero prior to a transition to a logic one state and: based on the length of time being longer than a predetermined threshold, provide for control of an output impedance by the impedance control device in accordance with a first scheme; and based on the length of time being shorter than said predetermined threshold, provide for one of: control of said output impedance in accordance with a second scheme; and no control of the output impedance by the impedance control device.

Abstract: Speed of plasma etching is regulated in regions prone to over-etching by providing an etch resistant structure, such as a metal saw bow, in the region. By adjusting dimensions, such as the length and width of the saw bow legs and an area defined by the saw bow legs, as well as a shape of the etch region through techniques such as chamfering, plasma etch speed in the region can be controlled with an intent to match the speed of etching in non-over-etched regions.

Abstract: A method is provided in a data processing system having second level address translation (SLAT) controlled by a hypervisor. In the method, hashes of all memory pages accessible by a guest OS are stored (set S). Also, hashes of all memory pages previously accessed by the guest OS are stored (set T). When the guest OS attempts an access to a memory page having executable code for which it does not have permission, an exception is generated. A hash of the memory page is compared with the hashes of set T and set S. If there is not a match within set T, then the guest OS has never attempted the requested operation before and suspicious behavior is reported. If there is not a match within set S, the requested operation is reported as illegal. In another embodiment, the memory page may be encrypted to prevent the guest OS from reading the memory page.